This card MUST be installed in Slot B!
Advanced FP Board, Base card P/N
08F3524, no FRU (Level 2)
Cypress CY7C128-35 (?)
Advanced FP Board, Daughtercard
P/N 08F3561 no FRU (Level 2)
Big chip is AD ADSP-1401 sequencer
* Advanced Floating-Point Accelerator [115,125,B25 only]
Note: There are two versions of this card:
- level 1 (#6814,61X6814) (bar code A117Kxxxxxx) can be used with either the original processor board (P/N 79X3766), or the Advanced Processor board (P/N 08F3639).
- level 2 (#6815,08F3589) (bar code A1206xxxxxx) use with RT PC Processor Board 79X3766, or RT PC Advanced Processor Board 08F3639, or RT PC Enhanced Advanced Processor Board 08F3587.
Charlie Sauer wrote:
There is an optional "Advanced Floating Point Accelerator"
(AFPA) card which uses an ADSP 3221 ALU, 3210 multiplier and 1401 sequencer. The microcode on the AFPA provides trigonometric and other functions. There is a gate array that goes between either of these and the ROMP-C fixed point processor. The gate array presents a 68020-like interface to the 68881 and presents a DMA-like interface to the ROMP, so that fixed point and floating point operations can proceed concurrently. I don't know of any externally available documentation on these other than the Hardware Technical Reference, SV21-8024. (Orderable at IBM branch offices.)
The original RT processor card has no built in floating point processor. An FPA for the original processor card is described in Scott M. Smith, "Floating Point Accelerator" in RT Personal Computer Technology SA23-1057, January 1986. That FPA uses an NS32081.
AIX provides a DMA-like floating point compatibility interface which is bound to the process at exec time so that object code can be compiled to be independent of the floating point hardware. This interface has sufficiently low overhead that AIX does not provide a direct interface to the 68881. A direct interface to the AFPA is provided. The compatibility interface is documented in AIX Operating System Technical Reference Version 2.1, SBOF-0135.
All of the above are designed to be compliant with IEEE P754 10.1.