Up to six processor ccards can be installed onto the multiprocessor bus on the Server 720. Each processor card has the following functions:
An Intel Pentium processor. Currently
announced are 100 MHz, 133 MHz, and 166 MHz options.
SMP 166Mhz Processor Card
P/N 94G6057(R) FRU 76H3545
Currently, the following processor cards are announced:
100 MHz (part #94G2724) - For all OS other than NW 4.1 SMP
Note: Of a maximum of six processors in the 720, the number
of earlier 166 MHz standard processor boards is limited to two. This
only applies to processor boards delivered as standard processors.
This limit of two 166 MHz standard processors is due to a limitation of
the power supply. These 166MHz boards draw current from the 5 V power
supply and not the 3.3 V supply as do the other processor boards. All 166
MHz optional processors boards (P/N 94G6057) are 3.3 V. They may be added
without a restriction.
To ensure highest performance, the processor and cache are designed
to operate with zero wait states. In addition, all processor cards are
fully symmetrical for main memory access, I/O, and interrupts. This means
that no single processor can be a bottleneck, for example, through having
In an SMP system, some data might be held within multiple processor caches. If this data is modified by one processor, then it needs to be updated in the other caches before another processor operates on out-of-date information. This is called cache coherency and is handled by the MESI (Modified, Exclusive, Shared or Invalid) protocol.
Each of the PC Server 720 processor cards has three levels of private cache. Lower level caches are typically very fast but also very expensive. In general, the closer to the processor, the faster and more expensive the cache will be.
The first, or L1 cache, is built into the Pentium processor. This is th first place the processor will look when it needs its next instruction or piece of data to operate on. If this data is not contained in L1, the system next searches the second level, or L2 cache. If the information is found in either of these locations, the processor can continue without incurring wait states. However, if the information is still not available from the L1 cache or the L2 cache, the processor will need to obtain it from main memory. Depending on the speed of the memory subsystem, it may take a few clock cycles for this transaction to complete.
When the information is retrieved from main memory, it is stored in a free cache location. If there are no free locations, then the new data replaces the least frequently used information currently stored in the cache.
Since the Server 720 uses performance-boosting write-back cache, this least frequently used data may have already been modified by the CPU and must, therefore be evicted first or written back to memory. In most systems, the processor would have to wait for that data to be written out before it could bring in a new line of cache.
The Server 720 takes the unique approach of adding a small six-line L3 cache to each processor card. The 720's L3 or victim cache allows that data to be quickly cleared from L2 to L3 making room for new information and allowing modified data to be written to main memory later during free bus cycles. In addition, this information is still available to be quickly accessed if needed in future cycles.
This approach improves the overall cache hit ratio with little additional cost while saving significant clock cycles during the write back or eviction process. Access to data in any of these three caches can be accomplished with zero wait states so the processor continues work on its applications without wasting time.
It may seem more effective to simply make the L2 cache much larger to increase the cache-hit ratio directly. However, since the cache memory tends to be expensive, the size of the L2 cache is carefully chosen to provide a high cache-hit rate at reasonable cost. As it takes time to search the cache for the required information, it is also possible to have a cache that is too large and too slow to respond to each request.
The carefully balanced cache design of the 720, however, provides for a high percentage of zero-wait states processing resulting in excellent multiprocessor performance.
Server 720 SMP 133MHz Processor Opt. II RETAIN: #H132301
Important Information if you have installed the IBM PC Server 720 SMP Option II.
OBI Processor Card P/N
The above Options are only supported with 'Novell NetWare V-3.12 V-4.1' or SMP operating system.
The origin 100MHz processor card (or cards) installed in the server must be removed before installing a server option. If you are not sure if one or more of the processor cards inside the server are one of the original 100MHz processor cards, do the following:
1. Remove a processor card from the server and locate the FRU P/N printed
on a label on the card.
Once you have completed steps 1 through 4 for all of the processor cards currently installed in the server, then you can install the new processor option.
Note 1.) The processor card 76H6852 (71G0692) should be exchanged with FRU P/N 76H6850 (75H9648) if NetWare SMP is installed. Do not replace the card if OS/2 or any other Operating System is installed, because this processor card FRU P/N 76H6850 (75H9684) is designed to work with NetWare SMP only !
From the EPRM:
-IMPORTANT- Please understand
PC Server 720 - Testing processors
Follow this procedure to isolate the failing processor:
Refer to the IBM PC Server HMM, publication number
S30H-2501-01, page 377, for additional information on error codes.