Realtime Interface Co-Processor

Firmware Technical Reference

Volume 1 - System Interfaces and Functions
Volume 2 - Functions

Volume 3 - Data Structures

Second Edition (July 1990)

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Table of Contents

  • Special Notices
  • Purpose
  • Audience
  • Organization
  • Related Publications
  • Reference Publications
  • Conventions

  • Part 1. Volume III - Data Structures

  • Chapter 10. Software Functions for the Realtime Interface Co-Processor, Multiport, and Multiport/2 Adapters
  • Task Management
  • Management Tools
  • Associated Interface Modules
  • Resource Blocks
  • Available Resources
  • Resource Block Definition
  • User Interface Rules
  • User-Requestable Interrupt Vectors (01h)
  • Random Access Memory (RAM) Storage (02h)
  • SCC/CIO Port Packages (03h)
  • DMA Channels (04h)
  • User Queues (05h)
  • Hardware Timers (06h)
  • Software Timers (07h)
  • RS-232-C Ports (08h)
  • SCC Ports (09h)
  • CIO Ports (0Ah)
  • RS-422-A Ports (0Bh)
  • Resource Conflicts Table
  • System Unit Communications
  • Associated Interface Modules
  • Additional Task Services
  • Associated Interface Modules
  • First-Level Interrupt Handling
  • Interrupt Handling
  • Hardware Interrupt Processing
  • Software Timer Interrupt Handling
  • Command Interrupt Handling
  • Software Interrupt Handling
  • Associated Interface Modules
  • Asynchronous Error Handling
  • List of Asynchronous Error Conditions
  • Realtime Control Microcode Asynchronous Error Handling
  • Application Task Error Handling
  • Associated Interface Modules
  • Chapter 11. Interrupt Vector Table Map for the Realtime Interface Co-Processor, Multiport, and Multiport/2 Adapters

  • Chapter 12. Software Functions for the Portmaster Adapter/A and Multiport Adapter, Model 2
  • Task Management
  • Management Tools
  • Associated Interface Modules
  • Resource Blocks
  • Resource Block Definition
  • User Interface Rules
  • User-Requestable Interrupt Vectors (01h)
  • Random Access Memory (RAM) Storage (02h)
  • DMA Channels (04h)
  • User Queues (05h)
  • Hardware Timers (06h)
  • Software Timers (07h)
  • SCC Ports (09h)
  • CIO Ports (0Ah)
  • Communications Port (0Ch)
  • Expanded Memory Pages Resource Block (0Dh)
  • Extended Service Hooks Resource Block (0Eh)
  • First-Level Interrupt Handling
  • Hardware Interrupt Processing
  • Software Timer Interrupt Handling
  • Hardware Timer Interrupt Handling
  • Command Interrupt Handling
  • Software Interrupt Handling
  • Associated Interface Modules
  • System Unit Interrupts
  • Associated Interface Modules
  • Peer Services
  • Realtime Control Microcode Peer Request Block
  • Realtime Control Microcode Peer Request Block Commands and Responses
  • Peer Services Communications
  • Peer Services Initialization
  • Peer Services Recovery
  • Command Interrupt Handling for Peer Requests
  • Disabling Peer Services
  • Additional Task Services
  • Associated Interface Modules
  • Asynchronous Error Handling
  • List of Asynchronous Error Conditions
  • Realtime Control Microcode Asynchronous Error Handling
  • Application Task Error Handling
  • Associated Interface Modules
  • Chapter 13. Interrupt Vector Table Map for the Portmaster Adapter/A and Multiport Adapter, Model 2

  • Special Notices

    References in this publication to IBM products, programs, or services do not imply that IBM intends to make these available in all countries in which IBM operates.

    Any reference to an IBM licensed program or other IBM product in this publication is not intended to state or imply that only IBM's program or other product may be used.

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    The following terms, DENOTED BY AN ASTERISK (*), used in this publication, are trademarks or service marks of IBM Corporation in the United States and/or other countries:


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    About This Book

    This book contains software technical reference information concerning the IBM Realtime Interface Co-processor Adapter, Multiport Adapter, Multiport/2 Adapter, Portmaster Adapter/A, and the Multiport Adapter, Model 2.

    Note:

    Technical reference information for the IBM X.25 Interface Co-Processor/2 adapter is in the IBM X.25 Interface Co-Processor/2 Technical Reference.

    Throughout the book, the term "co-processor adapter" refers to the above adapter types.


    Purpose

    This manual:


    Audience

    This book contains introductory and reference information for software designers, programmers, and anyone with a knowledge of programming who needs to understand the use and operation of the co-processor adapter.

    You should be familiar with the system unit, your application, and programming. Only the terms that apply specifically to the co-processor adapter are explained.


    Organization

    The IBM Realtime Interface Co-Processor Firmware Technical Reference is organized into three volumes.

    Volume I contains the following:

    Volume II contains the following:

    Volume III contains the following:


    Related Publications

    Related books in the Realtime Interface Co-Processor library are as follows:

    IBM Realtime Interface Co-Processor Guide to Operations

    Provides instructions for installing the Realtime Interface Co-Processor features. It also describes problem-determination procedures.

    IBM Realtime Interface Co-Processor Adapter Hardware Maintenance and Service

    Used to isolate and repair any failure of a field-replaceable unit (FRU). It provides step-by-step instructions for problem isolation to aid in identifying a FRU. Removal and replacement procedures are presented to complete repair.

    IBM Realtime Interface Co-Processor Multiport Adapter Guide to Operations

    Provides instructions for installing the Realtime Interface Co-Processor Multiport Adapter features. It also describes problem-determination procedures.

    IBM Realtime Interface Co-Processor Multiport Adapter Hardware Maintenance and Service

    Used to isolate and repair any failure of a field-replaceable unit (FRU). It provides step-by-step instructions for problem isolation to aid in identifying a FRU. Removal and replacement procedures are presented to complete repair.

    IBM Realtime Interface Co-Processor Multiport/2 Adapter Guide to Operations

    Provides instructions for installing the Realtime Interface Co-Processor Multiport/2 Adapter features. It also describes problem-determination procedures.

    IBM Realtime Interface Co-Processor Multiport/2 Adapter Hardware Maintenance and Service

    Used to isolate and repair any failure of a field-replaceable unit (FRU). It provides step-by-step instructions for problem isolation to aid in identifying a FRU. Removal and replacement procedures are presented to complete repair.

    IBM Realtime Interface Co-Processor Multiport Adapter, Model 2 Guide to Operations

    Provides instructions for installing the Realtime Interface Co-Processor Multiport Adapter, Model 2 features. It also describes problem-determination procedures.

    IBM Realtime Interface Co-Processor Portmaster Adapter/A Guide to Operations

    Provides instructions for installing the hardware necessary to use the Realtime Interface Co-Processor Portmaster Adapter/A and describes problem-determination procedures.

    Realtime Interface Co-Processor Portmaster Adapter/A, Multiport Adapter, Model 2 Hardware Maintenance Library

    Used to isolate and repair any failure of a field-replaceable unit (FRU) for the Portmaster Adapter/A or the Multiport Adapter, Model 2. It provides step-by-step instructions for problem isolation to aid in identifying a FRU. Removal and replacement procedures are presented to complete repair.

    IBM Realtime Interface Co-Processor DOS Support

    Provides information necessary to interface the co-processor adapter through the system unit DOS. It describes all functions, capabilities, and installation of the Realtime Interface Co-Processor DOS Support software.

    IBM Realtime Interface Co-Processor OS/2 Support

    Provides information necessary to interface the co-processor adapter through the system unit Operating System/2* (OS/2*). It describes all functions, capabilities, and installation of the Realtime Interface Co-Processor OS/2 Support software.

    Realtime Interface Co-Processor C Language Support User's Guide

    Describes the C Language Support product-&dasha productivity aid that allows programmers to develop code for the co-processor adapter and the system unit in the C Programming Language. This guide explains the C-interface routines and the method of compiling and linking C-tasks for the co-processor adapter and your system unit.

    IBM Realtime Interface Co-Processor Extended Services, Version 1.01

    Describes the Extended Services product-&dasha productivity aid that provides the system developer with a variety of services to ease the writing of systems applications for the Realtime Interface Co-Processor family of adapters. It includes numerous task, event, resource, and communications services that allow the system developer to concentrate on the application instead of the system.


    Reference Publications

    You may need to use one or more of the following publications for reference with this manual:


    Conventions


    Part 1. Volume III - Data Structures

    Volume III contains the following:


    Chapter 10. Software Functions for the Realtime Interface Co-Processor, Multiport, and Multiport/2 Adapters

    This chapter describes the following for the Realtime Interface Co-Processor, the Realtime Interface Co-Processor Multiport, and the Realtime Interface Co-Processor Multiport/2 adapters:

    Associated data structures and a list of associated interface modules are also included.

    For related information for the Realtime Interface Co-Processor Portmaster Adapter/A or the Realtime Interface Co-Processor Multiport Adapter, Model 2, see Chapter 12. "Software Functions for the Portmaster Adapter/A and Multiport Adapter, Model 2".


    Task Management

    The Realtime Control Microcode is the multitasking supervisor that is loaded to the co-processor adapter as task 0. The Realtime Control Microcode controls the execution of all application tasks on the co-processor adapter. There may be up to 253 concurrent tasks executing on any of 255 priorities.

    Management Tools

    Management tools used by the Realtime Control Microcode to supervise tasks are:

    Data Structures

    The Realtime Control Microcode and application tasks use data structures (control blocks) to communicate and control the actions and states of the application tasks. The task writer should be familiar with the following data structures:

    Interface Block (IB)

    Purpose:
    Used as the central communication control block between the co-processor adapter and the system unit

    Location:
    Page 0 starting at location 0440h

    Size:
    MAXTASK + 3Dh bytes

    Initialization:
    Bootstrap Loader microcode sets the following values during power-on/reset initialization:
    The following values are initialized by the system unit support software:
    The Realtime Control Microcode sets the following values at Realtime Control Microcode initialization time:

    The format of the interface block is as follows:

    
    +---------------------------------------------------------------+
    
    
    
    | Interface Block                                               |
    
    
    
    +--------+----------+-----------------------+-------------------+
    
    
    
    | Byte   | Field    | Description           | Comments          |
    
    |        | Name     |                       |                   |
    
    
    
    +--------+----------+-----------------------+-------------------+
    
    | 0440h  | PC       | Indicates which       |= 0h-FDh           |
    
    |        | Select   | task the system       | Select task or    |
    
    |        | Byte     | unit wants to         | Realtime Control  |
    
    |        |          | interrupt.  This      | Microcode         |
    
    |        |          | byte is written       | when co-processor |
    
    |        |          | by the system         | adapter           |
    
    |        |          | unit prior to         | interrupted by    |
    
    |        |          | interrupting the      | host computer.    |
    
    |        |          | co-processor          |= FEh              |
    
    |        |          | adapter.  After       | Error indicator   |
    
    |        |          | the Realtime          | set by            |
    
    |        |          | Control Microcode     | Realtime Control  |
    
    |        |          | or Bootstrap          | Microcode after an|
    
    |        |          | Loader has            | error is detected |
    
    |        |          | received the          | in a command.     |
    
    |        |          | interrupt, this       |= FFh              |
    
    |        |          | byte is reset to      | Byte is empty and |
    
    |        |          | either FEh (to        | used for interlock|
    
    |        |          | signal an error)      | purposes.         |
    
    |        |          | or FFh (to acknow-    | initialized to    |
    
    |        |          | ledge the             | FFh by Bootstrap  |
    
    |        |          | interrupt).           | Loader.           |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0441h  | INTID    | Indicates which       |= 0h-FDh           |
    
    |        |          | task (or asynchro-    | indicates which   |
    
    |        |          | nous error) is        | task is           |
    
    |        |          | interrupting the      | interrupting      |
    
    |        |          | system unit.          | system unit.      |
    
    |        |          | This byte is          |= FEh              |
    
    |        |          | written by the        | Asynchronous      |
    
    |        |          | Realtime Control      | error interrupts. |
    
    |        |          | Microcode or the      |= FFh              |
    
    |        |          | Bootstrap Loader      | Byte is empty and |
    
    |        |          | prior to interrupt-   | used for interlock|
    
    |        |          | ing the host          | purposes.         |
    
    |        |          | computer.  After      | Initialized to    |
    
    |        |          | the host computer     | FFh by Bootstrap  |
    
    |        |          | receives the inter-   | Loader.           |
    
    |        |          | rupt, this byte is    |                   |
    
    |        |          | reset to FFh.         |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0442h  | SUPVID   | Realtime Control      | Version of        |
    
    |        |          | Microcode identity    | Realtime Control  |
    
    |        |          | byte.                 | Microcode         |
    
    |        |          |                       | resident in       |
    
    |        |          |                       | co-processor      |
    
    |        |          |                       | adapter           |
    
    |        |          |                       | 00h = Realtime    |
    
    |        |          |                       | Control Microcode |
    
    |        |          |                       | not loaded        |
    
    |        |          |                       | 01h = V1.0        |
    
    |        |          |                       | 02h = V1.1        |
    
    |        |          |                       | 03h = V1.2        |
    
    |        |          |                       | 04h = V1.3        |
    
    |        |          |                       | 05h = V1.4        |
    
    |        |          |                       | 06h = V1.5        |
    
    |        |          |                       | 07h = V1.51       |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0443h  | CARDID   | Co-Processor adapter  | = 0h-Fh           |
    
    |        |          | number; set by system |                   |
    
    |        |          | unit support software.|                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0444h  | MAXTASK  | Highest task number.  | = 0h-FDh          |
    
    |        |          | Set by system unit    |                   |
    
    |        |          | support software.     |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0445h  | MAXPRI   | Lowest priority level | = 1h-FFh          |
    
    |        |          | (highest number).     |                   |
    
    |        |          | Set by system unit    |                   |
    
    |        |          | support software.     |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0446h  | MAXQUEUE | Highest user          | = 0h-FEh          |
    
    |        |          | queue number.         |                   |
    
    |        |          | Set by system unit    |                   |
    
    |        |          | support software.     |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0447h  | MAXTIME  | Highest software      | = 0h-FEh          |
    
    |        |          | timer number.         |                   |
    
    |        |          | Set by system unit    |                   |
    
    |        |          | support software.     |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0448h- | TCBTAB@  | Doubleword pointer    |                   |
    
    | 044Bh  |          | to TCB table (TCBTAB).|                   |
    
    |        |          | Initialized by the    |                   |
    
    |        |          | Realtime Control      |                   |
    
    |        |          | Microcode.            |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 044Ch- | PRIL@    | Doubleword pointer    |                   |
    
    | 044Fh  |          | to priority list      |                   |
    
    |        |          | (PRIL).               |                   |
    
    |        |          | Initialized by the    |                   |
    
    |        |          | Realtime Control      |                   |
    
    |        |          | Microcode.            |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0450h- | STORPTR  | First free storage    |                   |
    
    | 0453h  |          | block pointer.        |                   |
    
    |        |          | (0450h-0451h = segment|                   |
    
    |        |          | of next free storage  |                   |
    
    |        |          | block. 0452h-0453h =  |                   |
    
    |        |          | segment of previous   |                   |
    
    |        |          | free storage block.)  |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0454h- | Reserved | Word of zero.         | Must be           |
    
    | 0455h  |          |                       | zero              |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0456h- | HCD      | Hardware Config-      | *                 |
    
    | 0459h  |          | uration Descriptor    | (See              |
    
    |        |          | (HCD).  (0456h -      |  following        |
    
    |        |          | 0457h = HCD value.    |  discussion       |
    
    |        |          | 0458h - 0459h         |  of HCD)          |
    
    |        |          | = 00.) The HCD is     |                   |
    
    |        |          | a bit specific        |                   |
    
    |        |          | descriptor of the     |                   |
    
    |        |          | available resources   |                   |
    
    |        |          | on the co-processor   |                   |
    
    |        |          | adapter.  Initial-    |                   |
    
    |        |          | ized by the           |                   |
    
    |        |          | Bootstrap Loader.     |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 045Ah- | BCB@     | Pointer to offset     |                   |
    
    | 045Bh  |          | of first BCB in       |                   |
    
    |        |          | page zero (segment    |                   |
    
    |        |          | zero). Initialized    |                   |
    
    |        |          | by the Realtime       |                   |
    
    |        |          | Control Microcode.    |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 045Ch- | TASKTAB@ | Doubleword pointer to |                   |
    
    | 045Fh  |          | task table (TASKTAB). |                   |
    
    |        |          | Initialized by the    |                   |
    
    |        |          | Realtime Control      |                   |
    
    |        |          | Microcode.            |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0460h- | QUEUETAB@| Doubleword pointer    |                   |
    
    | 0463h  |          | to the user queue     |                   |
    
    |        |          | table (QUEUETAB).     |                   |
    
    |        |          | Initialized by the    |                   |
    
    |        |          | Realtime Control      |                   |
    
    |        |          | Microcode.            |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0464h- | TIMETAB@ | Doubleword pointer    |                   |
    
    | 0467h  |          | to the timer block    |                   |
    
    |        |          | list.  Initialized    |                   |
    
    |        |          | by the Realtime       |                   |
    
    |        |          | Control Microcode.    |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0468h- | RESERVED1| Reserved              | Must be           |
    
    | 046Bh  |          |                       | zero              |
    
    +--------+----------+-----------------------+-------------------+
    
    | 046Ch- | RESERVED2| Reserved              | Must be           |
    
    | 046Fh  |          |                       | zero              |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0470h- | RESERVED3| Reserved              | Must be           |
    
    | 0473h  |          |                       | zero              |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0474h- | RESERVED4| Reserved              | Must be           |
    
    | 0477h  |          |                       | zero              |
    
    +--------+----------+-----------------------+-------------------+
    
    | 0478h- | STORSIZE | Number of paragraphs  |                   |
    
    | 0479h  |          | of storage on this    |                   |
    
    |        |          | co-processor adapter. |                   |
    
    |        |          | Initially set by      |                   |
    
    |        |          | Bootstrap Loader.     |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 047Ah  | DB0ID    | Identifier of SCC     |                   |
    
    |        |          | port 0 electrical     |                   |
    
    |        |          | interface.            |                   |
    
    |        |          | Initially set by      |                   |
    
    |        |          | Bootstrap Loader.     |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 047Bh  | DB1ID    | Identifier of SCC     |                   |
    
    |        |          | port 1 electrical     |                   |
    
    |        |          | interface.            |                   |
    
    |        |          | Initially set by      |                   |
    
    |        |          | Bootstrap Loader.     |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    | 047Ch- | STATARRAY| Primary status byte   | **                |
    
    | nnnnh  |          | array. Primary status | (See              |
    
    |        |          | of each task and      |  following        |
    
    |        |          | Realtime Control      |  primary          |
    
    |        |          | Microcode.  One byte  |  status           |
    
    |        |          | for the Realtime      |  byte)            |
    
    |        |          | Control Microcode and |                   |
    
    |        |          | one byte for each     |                   |
    
    |        |          | possible task.  The   |                   |
    
    |        |          | size of the array =   |                   |
    
    |        |          | MAXTASK + 1.          |                   |
    
    |        |          |                       |                   |
    
    |        |          | Byte zero (Realtime   |                   |
    
    |        |          | Control Microcode     |                   |
    
    |        |          | Status Bytes)         |                   |
    
    |        |          | initialized to zero   |                   |
    
    |        |          | by Bootstrap Loader.  |                   |
    
    |        |          | All other bytes       |                   |
    
    |        |          | initialized to zero   |                   |
    
    |        |          | by the Realtime       |                   |
    
    |        |          | Control Microcode.    |                   |
    
    +--------+----------+-----------------------+-------------------+
    
    

    Hardware Configuration Descriptor (HCD) Bit Definition
    
    
    
     Name              Bit   Description
    
    ----------------------------------------------------------------
    
     SCC1 (Ports 2-3)   0    If this bit is set to one, SCC 1
    
                             is present and functioning.  If
    
                             this bit is cleared to 0,
    
                             SCC 1 is not present or not
    
                             functioning.
    
    
    
     SCC2 (Ports 4-5)   1    If this bit is set to one, SCC 2
    
                             is present and functioning.  If
    
                             this bit is cleared to 0,
    
                             SCC 2 is not present or not
    
                             functioning.
    
    
    
     SCC3 (Ports 6-7)   2    If this bit is set to one, SCC 3
    
                             is present and functioning.  If
    
                             this bit is cleared to 0,
    
                             SCC 3 is not present or not
    
                             functioning.
    
    
    
     CIO 1              3    If this bit is set to one, CIO 1
    
                             is present and functioning.  If
    
                             this bit is cleared to 0,
    
                             CIO 1 is not present or not
    
                             functioning.
    
    
    
     Reserved        4-15    Must be 0.
    
    

    The HCD identifies the hardware resources present in addition to SCC 0 and CIO 0. The HCD is normally used to determine the number of ports available on the co-processor adapter.

    Primary Status Byte Bit Definition
    
    
    
     Name     Bit   Description
    
    ----------------------------------------------------------------
    
     LOAD      0    Loaded.  This bit is set by the Realtime
    
                    Control Microcode when a task is loaded or
    
                    built.  It is reset when a task is unloaded.
    
    
    
     INIT      1    Initialized.  This bit is set by the
    
                    Realtime Control Microcode when a task
    
                    issues the "INITCOMP" Service Call (SVC).
    
                    It is reset when a task is stopped.
    
    
    
     RESTART/  2    For Task 0, bit on indicates that the
    
     INPUT          co-processor adapter is requesting a system
    
                    re-start of the system unit.  The system unit
    
                    should simulate the Ctrl+Alt+Del sequence
    
                    via software to cause the system unit to
    
                    restart.  It is reset when Task 0 is
    
                    initialized.
    
    
    
                    Tasks can use this bit to indicate that
    
                    input data is ready to be read by the system
    
                    unit.  The use of this bit is optional and
    
                    not checked by the Realtime Control
    
                    Microcode.  If the bit is used by a task,
    
                    the task is responsible for both setting and
    
                    resetting it.
    
    
    
     WATCHDOG  3    Watchdog Active if on (used by the Realtime
    
                    Control Microcode only; for task,
    
                    user-definable).  It is set when the
    
                    watchdog timer is active.
    
    
    
                    Tasks can use bit 3 to indicate that the
    
                    task is ready to receive data from the
    
                    system unit.  The use of this bit is
    
                    optional and not checked by the Realtime
    
                    Control Microcode.  If used by a task, it is
    
                    responsible for setting and resetting it.
    
    
    
     ERROR     4    Bit on indicates that the task has detected an
    
                    error.  The task's Secondary Status should
    
                    be examined to determine the cause of the
    
                    error.  This bit is reset by the Realtime
    
                    Control Microcode after receipt of a command
    
                    directed to this task from the system unit.
    
                    It is set by the task.
    
    
    
     Name     Bit   Description
    
    ----------------------------------------------------------------
    
     STATUS    5    Secondary Status available.  This bit is set
    
                    by the task and is used to indicate that the
    
                    data in the task's secondary status buffer
    
                    is valid.  The bit is reset by the Realtime
    
                    Control Microcode after receipt of a command
    
                    directed to this task from the system unit.
    
    
    
     OUTPUT    6    Output buffer busy.  This bit is set by the
    
                    Realtime Control Microcode when a task
    
                    receives a command.  It indicates that the
    
                    task's output buffer should not be
    
                    overwritten.  This bit should be cleared by
    
                    the task.
    
    
    
     BUSY      7    Busy.  A task cannot receive commands from
    
                    the system unit when this bit is set.  It is
    
                    set by the Realtime Control Microcode when a
    
                    task receives a command.  This is the only
    
                    interlock type bit that must be tested
    
                    before single-byte commands are issued.  The
    
                    commands that require parameters in the
    
                    output buffer must also check the output
    
                    busy bit before the parameters are written
    
                    to the output buffer.
    
    

    Buffer Control Block (BCB)

    Purpose:
    Used by system unit application program, tasks, and the Realtime Control Microcode to pass data, control, and direct actions of the task. Provides pointers to data and status buffers for each task

    Location:
    Realtime Control Microcode storage on page 0 (segment 0)

    Size:
    (MAXTASK + 1) * 16 bytes. There is one BCB for the Realtime Control Microcode and for each task as specified by MAXTASK.

    Initialization:
    Initial value set by task

    The format of a BCB is as follows:

    
    +------------------------------------------------------------+
    
    
    
    | Buffer Control Block                                       |
    
    
    
    +------+---------+-------------------------+-----------------+
    
    
    
    | Byte | Field   | Description             | Comments        |
    
    |      | Name    |                         |                 |
    
    
    
    +------+---------+-------------------------+-----------------+
    
    | 00h  | CMD     | Command field.  This    | Valid command   |
    
    |      |         | byte is set by system   | values are      |
    
    |      |         | unit applications and   | task specific.  |
    
    |      |         | interrogated by         | See "System     |
    
    |      |         | application tasks.      | Unit Commands"  |
    
    |      |         |                         | in Volume I     |
    
    |      |         |                         | for the         |
    
    |      |         |                         | commands        |
    
    |      |         |                         | supported by    |
    
    |      |         |                         | the Realtime    |
    
    |      |         |                         | Control         |
    
    |      |         |                         | Microcode.      |
    
    +------+---------+-------------------------+-----------------+
    
    | 01h- | STATLNG | Length of the task's    |                 |
    
    | 02h  |         | secondary status field. |                 |
    
    +------+---------+-------------------------+-----------------+
    
    | 03h- | STATOFF | Offset of the secondary |                 |
    
    | 04h  |         | status field in a page. |                 |
    
    +------+---------+-------------------------+-----------------+
    
    | 05h  | STATPAG | Page number of the      |                 |
    
    |      |         | secondary status field. |                 |
    
    +------+---------+-------------------------+-----------------+
    
    | 06h- | INLNG   | Length of the input     |                 |
    
    | 07h  |         | buffer.                 |                 |
    
    +------+---------+-------------------------+-----------------+
    
    | 08h- | INOFF   | Offset of the input     |                 |
    
    | 09h  |         | buffer in a page.       |                 |
    
    +------+---------+-------------------------+-----------------+
    
    | 0Ah  | INPAG   | Page number of the start|                 |
    
    |      |         | of the input buffer.    |                 |
    
    +------+---------+-------------------------+-----------------+
    
    | 0Bh- | OUTLNG  | Length of the output    |                 |
    
    | 0Ch  |         | buffer.                 |                 |
    
    +------+---------+-------------------------+-----------------+
    
    | 0Dh- | OUTOFF  | Offset of the output    |                 |
    
    | 0Eh  |         | buffer in a page.       |                 |
    
    +------+---------+-------------------------+-----------------+
    
    | 0Fh  | OUTPAG  | Page number of the start|                 |
    
    |      |         | of the output buffer.   |                 |
    
    +------+---------+-------------------------+-----------------+
    
    

    Notes:

    1. The Task Status, Input, and Output buffers are normally in the task load module or in acquired storage. The BCB provides a central location for various system unit applications and other tasks to locate these buffers.

    2. The pointers to the buffers are in page:offset format for more direct access from system unit applications.

    3. The terms "input" and "output" are used as viewed from the system unit. The input buffer is normally used to pass data from a task to a system unit application. The output buffer is normally used to pass data from a system unit application to a task.

    Task 0 Secondary Status Field Definition

    The location of the secondary status buffer is contained in the "status and control" pointer in the Task 0 buffer control block (BCB).

    The Task 0 secondary status field is defined in the following table. The error codes for the system unit to Task 0 commands are located in the column where byte 0 equals 02h.

    
    +-------------------------------------------------------------+
    
    
    
    | Task 0 Secondary Status Field                               |
    
    
    
    +--------+-------------+------------------------+-------------+
    
    
    
    | Byte 0 | Definition  | Byte 1                 | Bytes 2 - 5 |
    
    
    
    +--------+-------------+------------------------+-------------+
    
    | 00h    | No error    | Undefined              | Undefined   |
    
    +--------+-------------+------------------------+-------------+
    
    | 01h    | Power-on    | 01h processor error    | Undefined   |
    
    |        | diagnostic  | 02h RAM error          | offset      |
    
    |        | tests       |                        | and segment |
    
    |        | errors      |                        | of failing  |
    
    |        |             |                        | bytes       |
    
    |        |             | 03h checksum error     | Undefined   |
    
    |        |             | 04h CIO 0 error        | Undefined   |
    
    |        |             | 05h SCC 0 error        | Undefined   |
    
    |        |             | 06h Shared storage     | Undefined   |
    
    |        |             |     interface chip     |             |
    
    |        |             |     error              |             |
    
    |        |             | 07h Parity check error | Undefined   |
    
    |        |             | 08h DMA allocation     | Undefined   |
    
    |        |             |     error              |             |
    
    |        |             | 09h CIO 1 error        | Undefined   |
    
    |        |             | 0Ah SCC 1 error        | Undefined   |
    
    |        |             | 0Bh SCC 2 error        | Undefined   |
    
    |        |             | 0Ch SCC 3 error        | Undefined   |
    
    +--------+-------------+------------------------+-------------+
    
    | 02h    | System unit | 01h Non-valid command  | Undefined   |
    
    |        | application | 02h Insufficient       | Undefined   |
    
    |        | programs to |     storage            |             |
    
    |        | Task 0      | 03h Non-valid command  | Undefined   |
    
    |        | command     |     data               |             |
    
    |        | errors      | 04h Non-valid task     | Undefined   |
    
    |        |             |     header             |             |
    
    |        |             | 05h Non-valid task     | Undefined   |
    
    |        |             |     number             |             |
    
    |        |             | 06h Task previously    | Undefined   |
    
    |        |             |     loaded             |             |
    
    |        |             | 07h Task previously    | Undefined   |
    
    |        |             |     started            |             |
    
    |        |             | 08h Non-valid task     | Undefined   |
    
    |        |             |     priority           |             |
    
    |        |             | 09h Non-valid command  | Undefined   |
    
    |        |             |     sequence           |             |
    
    |        |             | 0Ah Non-valid interface| Undefined   |
    
    |        |             |     block data         |             |
    
    |        |             | 0Bh Task stopped by    | Undefined   |
    
    |        |             |     debug facility     |             |
    
    |        |             | 0Ch Task previously    | Undefined   |
    
    |        |             |     stopped or not     |             |
    
    |        |             |     started            |             |
    
    |        |             | 0Dh Task is permanent  | Undefined   |
    
    +--------+-------------+------------------------+-------------+
    
    | 03h    | Non-valid   | Currently              | Offset:     |
    
    |        | Operation   | executing              | Segment     |
    
    |        | Code        | task number            | of next     |
    
    |        |             |                        | sequential  |
    
    |        |             |                        | instruction |
    
    +--------+-------------+------------------------+-------------+
    
    | 04h    | Parity      | Currently              | Offset:     |
    
    |        | error       | executing              | Segment     |
    
    |        |             | task number            | of next     |
    
    |        |             |                        | sequential  |
    
    |        |             |                        | instruction |
    
    +--------+-------------+------------------------+-------------+
    
    | 05h    | Watchdog    | Currently              | Offset:     |
    
    |        | Timer       | executing              | Segment     |
    
    |        | timed out   | task number            | of next     |
    
    |        |             |                        | sequential  |
    
    |        |             |                        | instruction |
    
    +--------+-------------+------------------------+-------------+
    
    | 06h    | System unit | Undefined              | Undefined   |
    
    |        | computer    |                        |             |
    
    |        | cannot be   |                        |             |
    
    |        | interrupted |                        |             |
    
    +--------+-------------+------------------------+-------------+
    
    | FFh    | System      | Requesting             | Undefined   |
    
    |        | restart     | task number            |             |
    
    |        | request     |                        |             |
    
    +--------+-------------+------------------------+-------------+
    
    

    Task Table (TASKTAB)

    Purpose:
    Control block to point to the task header of each task

    Location:
    Realtime Control Microcode storage

    Size:
    (MAXTASK * 2) + 2 bytes

    Initialization:
    All values initialized to zeros

    The format of the TASKTAB is as follows:

    
    +-------------------------------------------------------------+
    
    
    
    | Task Table                                                  |
    
    
    
    +----------+--------+-------------------+---------------------+
    
    
    
    | Byte     | Field  | Description       | Comments            |
    
    |          | Name   |                   |                     |
    
    
    
    +----------+--------+-------------------+---------------------+
    
    | 00h-     | Task 0 | Segment value of  |                     |
    
    | 01h      |        | Realtime Control  |                     |
    
    |          |        | Microcode header  |                     |
    
    +----------+--------+-------------------+---------------------+
    
    | 02h-     | Task 1 | Segment value     | 0 = task not loaded |
    
    | 03h      |        | location of task  | or built            |
    
    |          |        | header for Task 1 |                     |
    
    +----------+--------+-------------------+---------------------+
    
    | 04h-     | Task 2 | Segment value     | 0 = task not loaded |
    
    | 05h      |        | location of task  | or built            |
    
    |          |        | header for Task 2 |                     |
    
    +----------+--------+-------------------+---------------------+
    
    | .        | .      | .                 |                     |
    
    | .        | .      | .                 |                     |
    
    | .        | .      | .                 |                     |
    
    +----------+--------+-------------------+---------------------+
    
    |(MAXTASK* | Task   | Segment value     | 0 = task not loaded |
    
    | 2)       | MAXTASK| location of task  | or built            |
    
    |          |        | header for Task   |                     |
    
    |          |        | MAXTASK           |                     |
    
    +----------+--------+-------------------+---------------------+
    
    

    Task Control Block Table (TCBTAB)

    Purpose:
    Control block to point to TCB for each task

    Location:
    Realtime Control Microcode storage

    Size:
    (MAXTASK * 2) + 2 bytes

    Initialization:
    All values initialized to 0

    The format of the TCBTAB is as follows:

    
    +--------------------------------------------------------------+
    
    
    
    | Task Control Block Table                                     |
    
    
    
    +---------+--------+--------------------+----------------------+
    
    
    
    | Byte    | Field  | Description        | Comments             |
    
    |         | Name   |                    |                      |
    
    
    
    +---------+--------+--------------------+----------------------+
    
    | 00h-01h | Task 0 | Always 0 and exists|                      |
    
    |         |        | only for ease of   |                      |
    
    |         |        | access into table. |                      |
    
    |         |        | Table entry =      |                      |
    
    |         |        | TCBTAB@ + (2 *     |                      |
    
    |         |        | TASKNUM)           |                      |
    
    +---------+--------+--------------------+----------------------+
    
    | 02h-03h | Task 1 | Points to TCB of   | 0 = task does not    |
    
    |         |        | Task 1             | exist or not started |
    
    +---------+--------+--------------------+----------------------+
    
    | 04h-05h | Task 2 | Points to TCB of   | 0 = task does not    |
    
    |         |        | Task 2             | exist or not started |
    
    +---------+--------+--------------------+----------------------+
    
    | .       | .      |                    |                      |
    
    | .       | .      |                    |                      |
    
    | .       | .      |                    |                      |
    
    +---------+--------+--------------------+----------------------+
    
    |(MAXTASK*| Task   | Points to TCB of   | 0 = task does not    |
    
    |2)       | MAXTASK| Task MAXTASK       | exist or not started |
    
    +---------+--------+--------------------+----------------------+
    
    

    Task Control Block (TCB)

    Purpose:
    Used to communicate information about the task

    Location:
    Realtime Control Microcode storage

    Size:
    14h bytes for each task TSKN, TPRI, CVECT, SSEG, and SPTR are initialized from the task header. Parent task number is set when a "child" task is built. Other values are initialized to 0.

    Initialization:
    Built from the task header as a result of the Start SVC or Start Task command.

    The format of a TCB is as follows:

    
    +-------------------------------------------------------------+
    
    
    
    | Task Control Block                                          |
    
    
    
    +-------+---------+------------------------+------------------+
    
    
    
    | Byte  | Field   | Description            | Comments         |
    
    |       | Name    |                        |                  |
    
    
    
    +-------+---------+------------------------+------------------+
    
    | 00h-  | NEXT    | Next TCB pointer.      |                  |
    
    | 01h   |         | Points to TCB of next  |                  |
    
    |       |         | dispatchable task in   |                  |
    
    |       |         | list.  Points to this  |                  |
    
    |       |         | TCB if only task on    |                  |
    
    |       |         | this priority.  Set by |                  |
    
    |       |         | the Realtime Control   |                  |
    
    |       |         | Microcode.  Task must  |                  |
    
    |       |         | not modify this field. |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 02h-  | PREV    | Previous TCB pointer.  |                  |
    
    | 03h   |         | Points to previous TCB |                  |
    
    |       |         | in list.  Points to    |                  |
    
    |       |         | this TCB if this is    |                  |
    
    |       |         | only task on this      |                  |
    
    |       |         | priority.  Set by the  |                  |
    
    |       |         | Realtime Control       |                  |
    
    |       |         | Microcode.  Task must  |                  |
    
    |       |         | not modify this field. |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 04h   | TSKN    | Task number.  Task     | = 01h - MAXTASK  |
    
    |       |         | must not modify.       |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 05h   | TPRI    | Task priority.  Task   | = 01h - MAXPRI   |
    
    |       |         | must not modify.       |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 06h   | RETCODE | Return code of error.  |                  |
    
    |       |         | See SVC STATUS         |                  |
    
    |       |         | description for code   |                  |
    
    |       |         | definition.            |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 07h   | STB     | State byte.  Task      | *(see following  |
    
    |       |         | must not modify.       |   description)   |
    
    +-------+---------+------------------------+------------------+
    
    | 08h-  | PSTCD   | Post code.  Indicates  | **(see following |
    
    | 09h   |         | most recent reason why |    description)  |
    
    |       |         | this task was posted.  |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 0Ah   | POSTFLAG| Post flag to indicate  |                  |
    
    |       |         | that task has been     |                  |
    
    |       |         | posted.  It is task's  |                  |
    
    |       |         | responsibility to      |                  |
    
    |       |         | check and clear.       |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 0Bh   | PARENT  | Parent task number.    |                  |
    
    |       |         | If this task is a      |                  |
    
    |       |         | parent task, indicates |                  |
    
    |       |         | number of child tasks. |                  |
    
    |       |         | Set by "Build" SVC and |                  |
    
    |       |         | used for error recovery|                  |
    
    |       |         | purposes. Task must not|                  |
    
    |       |         | modify.                |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 0Ch-  | CVECT   | Command vector offset. |                  |
    
    | 0Dh   |         | Vector to be called    |                  |
    
    |       |         | when a command is      |                  |
    
    |       |         | received from the host |                  |
    
    |       |         | computer. Task should  |                  |
    
    |       |         | not modify if command  |                  |
    
    |       |         | to that task can occur.|                  |
    
    +-------+---------+------------------------+------------------+
    
    | 0Eh-  | CMDVEC  | Command vector segment.|                  |
    
    | 0Fh   |         | Task should not modify |                  |
    
    |       |         | if command to that task|                  |
    
    |       |         | can occur.             |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 10h-  | SSEG    | Stack segment for      |                  |
    
    | 11h   |         | this task.  Task       |                  |
    
    |       |         | must not modify.       |                  |
    
    +-------+---------+------------------------+------------------+
    
    | 12h-  | SPTR    | Stack pointer value    |                  |
    
    | 13h   |         | for this task.  Task   |                  |
    
    |       |         | must not modify.       |                  |
    
    +-------+---------+------------------------+------------------+
    
    

    State Byte (STB) Bit Definition
    
    ----------------------------------------------------------
    
      Bit        Meaning
    
    ----------------------------------------------------------
    
      0          If 1, task is queued
    
                 If 0, task is waiting (not queued)
    
    
    
      1          If 1, task suspended
    
                 If 0, task not suspended
    
    
    
      2-5        Not Used
    
    
    
      6          If 1, task is permanent
    
                 If 0, task is not permanent
    
    
    
      7          If 1, task is a parent task
    
                 If 0, task is not parent task
    
    

    Post Code (PSTCD) Bit Definition
    
    
    
    ------------------------------------------------------------------
    
      Bit        Meaning (suggested only, no data checks are made).
    
    ------------------------------------------------------------------
    
      0          POST.  Posted by task x.  The task ID for task is
    
                 in bits 8-15 of the Post Code.  Bits 1-7 can
    
                 be used for unique user codes.
    
    
    
      1          NEWCMD.  A new command is in the command buffer.
    
    
    
      2          Timer expired
    
    
    
      3          Posted by I/O interrupt handler
    
    
    
      4-7        User defined
    
    
    
      8-15       Posting task number
    
    

    Task Header

    Purpose:
    Used to pass task's initial parameters to the Realtime Control Microcode. Built by task writer or other task.

    Location:
    At location 0 in the task load module. Task header must be in the same segment as the task's resource blocks.

    Size:
    1Ch bytes. One per task.

    Initialization:
    Initial value task defined

    The format of a task header is as follows:

    
    +------------------------------------------------------------+
    
    
    
    | Task Header                                                |
    
    
    
    +------+------------+---------------------------+------------+
    
    
    
    | Byte | Field Name | Description               | Comments   |
    
    
    
    +------+------------+---------------------------+------------+
    
    | 00h- | TASKLNG1   | First 4 bytes = 32-bit    |            |
    
    | 01h  |            | module length.  Read by   |            |
    
    |      |            | loader when task is       |            |
    
    |      |            | loaded.  Set by loader    |            |
    
    |      |            | for .EXE files.           |            |
    
    +------+------------+---------------------------+------------+
    
    | 02h- | TASKLNG2   | Must be coded in source   |            |
    
    | 03h  |            | file for .COM files.      |            |
    
    +------+------------+---------------------------+------------+
    
    | 04h  | TASKNUM    | Task number.  Set by      |            |
    
    |      |            | Applications Loader       |            |
    
    |      |            | Utility or build task.    |            |
    
    +------+------------+---------------------------+------------+
    
    | 05h  | Reserved   | Reserved.                 | Must be 0  |
    
    +------+------------+---------------------------+------------+
    
    | 06h  | TASKID     | Task identification.      |            |
    
    | 07h  |            | User-defined.             |            |
    
    +------+------------+---------------------------+------------+
    
    | 08h  | TASKPRI    | Task priority.            | 1 - MAXPRI |
    
    |      |            | User-defined.             |            |
    
    +------+------------+---------------------------+------------+
    
    | 09h  | Reserved   | Reserved for co-processor | Must be 0  |
    
    |      |            | adapter Application Debug | when task  |
    
    |      |            | Utility use.              | is started |
    
    +------+------------+---------------------------+------------+
    
    | 0Ah- | CMDOFF     | Command vector offset.    |            |
    
    | 0Bh  |            | User-defined.  This is    |            |
    
    |      |            | the offset of the task    |            |
    
    |      |            | command handler routine.  |            |
    
    |      |            | This routine is called    |            |
    
    |      |            | (via a Far Call) by the   |            |
    
    |      |            | Realtime Control Micro-   |            |
    
    |      |            | code when a system unit   |            |
    
    |      |            | application presents a    |            |
    
    |      |            | command to the task.      |            |
    
    |      |            | Tasks should treat this   |            |
    
    |      |            | routine as an interrupt   |            |
    
    |      |            | handler, preserving the   |            |
    
    |      |            | machine state and limit-  |            |
    
    |      |            | ing processing, and       |            |
    
    |      |            | return to the Realtime    |            |
    
    |      |            | Control Microcode via a   |            |
    
    |      |            | Far Return.               |            |
    
    +------+------------+---------------------------+------------+
    
    | 0Ch- | CMDSEG     | Command vector segment.   |            |
    
    | 0Dh  |            |                           |            |
    
    +------+------------+---------------------------+------------+
    
    | 0Eh- | INITOFF    | Initial entry vector      |            |
    
    | 0Fh  |            | offset.  User-defined.    |            |
    
    |      |            | This is the offset of     |            |
    
    |      |            | the task's initial entry  |            |
    
    |      |            | point.  The Realtime      |            |
    
    |      |            | Control Microcode         |            |
    
    |      |            | dispatches the task at    |            |
    
    |      |            | this address when the     |            |
    
    |      |            | task is started.  The     |            |
    
    |      |            | task executes here at     |            |
    
    |      |            | task initialization time. |            |
    
    +------+------------+---------------------------+------------+
    
    | 10h- | INITSEG    | Initial entry vector      |            |
    
    | 11h  |            | segment.                  |            |
    
    +------+------------+---------------------------+------------+
    
    | 12h- | DATASEG    | Data segment value.       |            |
    
    | 13h  |            |                           |            |
    
    +------+------------+---------------------------+------------+
    
    | 14h- | STKSEG     | Stack segment value.      |            |
    
    | 15h  |            |                           |            |
    
    +------+------------+---------------------------+------------+
    
    | 16h- | STKPTR     | Stack pointer value.      |            |
    
    | 17h  |            | User-defined.             |            |
    
    +------+------------+---------------------------+------------+
    
    | 18h- | RBPTR      | Resource block chain      | Must be    |
    
    | 19h  |            | pointer.  Task must       | 0 at start |
    
    |      |            | not modify.               | time.      |
    
    +------+------------+---------------------------+------------+
    
    | 1Ah- | HRDEXT     | Extension offset.         | 0 indicates|
    
    | 1Bh  |            | Offset within same        | no         |
    
    |      |            | segment header for        | extension. |
    
    |      |            | user-defined header       |            |
    
    |      |            | information.              |            |
    
    +------+------------+---------------------------+------------+
    
    | 1Ch- |            | Resource block area       | The        |
    
    | nnh  |            | (size as required).       | resource   |
    
    |      |            |                           | blocks     |
    
    |      |            |                           | must be in |
    
    |      |            |                           | the same   |
    
    |      |            |                           | segment    |
    
    |      |            |                           | as the task|
    
    |      |            |                           | header.    |
    
    |      |            |                           | Although   |
    
    |      |            |                           | not        |
    
    |      |            |                           | required,  |
    
    |      |            |                           | the        |
    
    |      |            |                           | resource   |
    
    |      |            |                           | blocks     |
    
    |      |            |                           | normally   |
    
    |      |            |                           | the task   |
    
    |      |            |                           | header.    |
    
    +------+------------+---------------------------+------------+
    
    

    Priority Queue Scheduling

    When a task is started, its priority is established from the priority byte in its task header. This is the priority that the task is assigned for dispatch by the Realtime Control Microcode; the lower the value, the higher the priority for dispatching.

    For example, tasks at priority 2 are dispatched when there are dispatchable tasks on priorities 2 and 7. As long as there is a task dispatchable at a priority higher than Task A's priority, Task A is not dispatched. Task A may still receive interrupts because interrupts, if enabled, are a higher priority than the dispatch of tasks; but if Task A posts itself in an interrupt handler, it is not dispatched until its priority is the highest priority with dispatchable tasks. Furthermore, if a higher priority task is posted, that task is given control over Task A. The priority assigned to tasks is very important in the operation of the tasks. Higher priority tasks should relinquish control ("wait" themselves) if they do not need to be on the dispatch queue. This allows the lower priority tasks to execute.

    The Realtime Control Microcode executes a dispatch cycle when a task requests an SVC. The Realtime Control Microcode also attempts to dispatch higher priority tasks at the end of the Realtime Control Microcode's first level interrupt handlers (FLIHs), which execute when hardware interrupts are generated (referred to as preemptive dispatches). The time slice timer is one example of a hardware interrupt that can cause a preemptive dispatch cycle to occur. This timer is programmed by the Realtime Control Microcode to interrupt 10 milliseconds after the most recent dispatch cycle.

    If a task executes a 10-millisecond code path with no SVCs, the time slice timer expires and forces a preemptive dispatch cycle.

    Changing a task's priority in its header after it is started does not change its priority. When a task is started, a copy of the task's priority is made into the task's TCB. If the priority of a task needs to be changed, it must be changed in the TCB. This change of priority does not take effect until the task is put onto the dispatch queue. To ensure that the new priority takes effect, the task can be suspended, the priority changed in the TCB, and the task resumed. It is important that the task's priority is not changed at a time when it could be put on the dispatch queue. Instead, suspending the task prevents that from occurring.

    Task State Control

    The following diagrams describe the transitions between the various task states:

    
                 +----------------------------------------+-----------+
    
                 |    Command or Supervisor Call          | Realtime  |
    
                 |                                        | Control   |
    
                 |                                        | Microcode |
    
                 |                                        | Action    |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | State      | Load or | Unload   | Start   | Stop    | Dispatch  |
    
    | Comb.      | Build   |          |         |         |           |
    
    | (Note 3)   |         |          |         |         |           |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | Unloaded   | Loaded  | Error    | Error   | Error   | Cannot    |
    
    |            | and not |          |         |         | happen    |
    
    |            | started |          |         |         |           |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | Loaded     | Error   | Unloaded | Loaded  | Loaded  | Cannot    |
    
    | and not    |         |          | &       | & not   | happen    |
    
    | started    |         |          | started | started |           |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | Loaded,    | Error   | Unloaded | Error   | Loaded  | Cannot    |
    
    | started, & |         |          |         | & not   | happen    |
    
    | waiting    |         |          |         | started |           |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | Loaded,    | Error   | Unloaded | Error   | Loaded  | Loaded,   |
    
    | started, & |         |          |         | & not   | started,  |
    
    | posted     |         |          |         | started | posted &  |
    
    |            |         |          |         |         | executing |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | Loaded,    | Error   | Unloaded | Error   | Loaded  | Cannot    |
    
    | started,   |         |          |         | & not   | happen    |
    
    | posted, &  |         |          |         | started |           |
    
    | executing  |         |          |         |         |           |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | Loaded,    | Error   | Unloaded | Error   | Loaded  | Cannot    |
    
    | started,   |         |          |         | & not   | happen    |
    
    | posted, &  |         |          |         | started |           |
    
    | suspended  |         |          |         |         |           |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | Loaded,    | Error   | Unloaded | Error   | Loaded  | Cannot    |
    
    | started,   |         |          |         | & not   | happen    |
    
    | waiting, & |         |          |         | started |           |
    
    | suspended  |         |          |         |         |           |
    
    +------------+---------+----------+---------+---------+-----------+
    
    | Resident   | Loaded  | Error    | Error   | Error   | Cannot    |
    
    |            | and not |          |         |         | happen    |
    
    |            | started |          |         |         |           |
    
    +------------+---------+----------+---------+---------+-----------+
    
    
    
                 +------------------------------------------+------------+
    
                 |    Supervisor Call or Service Interrupt  | Supervisor |
    
                 |                                          | Call       |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | State      | Post     | Wait    | Suspend   | Resume  | Terminate  |
    
    | Comb.      |          |         |           |         | but Remain |
    
    | (Note 2)   |          |         |           |         | resident   |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | Unloaded   | Error    | Cannot  | Error     | Error   | Cannot     |
    
    |            |          | happen  |           |         | happen     |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | Loaded &   | Error    | Cannot  | Error     | Error   | Cannot     |
    
    | not        |          | happen  |           |         | Happen     |
    
    | started    |          |         |           |         |            |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | Loaded,    | Loaded,  | Cannot  | Loaded,   | Error   | Cannot     |
    
    | started, & | started, | happen  | started,  |         | happen     |
    
    | waiting    | & posted |         | waiting & |         |            |
    
    |            |          |         | suspended |         |            |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | Loaded,    | No       | Cannot  | Loaded,   | Error   | Cannot     |
    
    | started, & | Action   | happen  | started,  |         | happen     |
    
    | posted     |          | **      | posted &  |         | (Note 2)   |
    
    |            |          |         | suspended |         |            |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | Loaded,    | No       | Loaded, | Loaded,   | Error   | Resident   |
    
    | started,   | action   | started | started,  |         |            |
    
    | posted, &  |          | &       | posted &  |         |            |
    
    | executing  |          | waiting | suspended |         |            |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | Loaded,    | No       | Cannot  | Error     | Loaded, | Cannot     |
    
    | started,   | action   | happen  |           | started | happen     |
    
    | posted, &  |          |         |           | &       |            |
    
    | suspended  |          |         |           | posted  |            |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | Loaded,    | Loaded,  | Cannot  | Error     | Loaded, | Cannot     |
    
    | started,   | started, | happen  |           | started | happen     |
    
    | waiting, & | posted & |         |           | &       |            |
    
    | suspended  | suspended|         |           | waiting |            |
    
    +------------+----------+---------+-----------+---------+------------+
    
    | Resident*  | Error    | Cannot  | Error     | Error   | Cannot     |
    
    | (Note 1)   |          | happen  |           |         | happen     |
    
    ------------+----------+---------+-----------+---------+------------+
    
    

    Notes:

    1. Another task can be loaded with the same task number but not in the same storage.

    2. Only the running task can issue a "Wait" or "Stay Resident" SVC to itself.

    3. These are not proper states but are combinations of states.

    Loading a Task

    There are two ways a task can be created:

    Both of these methods will:

    None of these methods requires that the task header information be available. When a task is loaded by the Application Loader Utility, the task (including the header) is not actually written into the task space until after the Request Task Load command (or similar, such as Request Task Load with boundary or Request Task Load Low) is completed. If a system unit application program needs storage on the co-processor adapter, it is permissible to "LOAD" a task of the needed size and utilize the storage as necessary. The Request Task Load command allocates the storage to the task number, but the storage is not checked for valid header characteristics unless the task is started.

    Parent/Child/Peer Task Relationships

    When a co-processor adapter task performs a Build SVC, it may build either a child task or a peer task. If a child task is built, the building task is a parent task. Child tasks cannot build child tasks. There are no restrictions on a task that builds a peer except that the peer resides in acquired storage.

    The acquired storage is taken away from the building task when the peer is built and assigned to the peer task. After a peer task is built, there is no linkage by the Realtime Control Microcode between a building task and the peer task it built. This is not true of a parent and child relationship. A parent task may not be stopped or unloaded without the child task also being stopped and unloaded.

    If a child task identifies itself as permanent when it does its Initcomp (initialization complete) SVC, the parent task is also marked as permanent and there is no supported mechanism to change this permanent status. A child task is not marked as permanent on the basis of the parent task being permanent.

    Unloading a Task

    The specified task is unloaded from the co-processor adapter storage. If the task is not already stopped, it is stopped as described in the Stop SVC. The task's resident storage is returned to the free memory pool and the loaded bit in the task's primary status byte in the interface block is reset to 0. If any errors are detected, the command is not performed.

    Starting and Initializing a Task

    After a task is loaded or built in the co-processor adapter, it must be started before it is dispatchable.

    At "start" time, the task is given control at the initial entry point, as defined in the task's header. The task should set up its buffers and perform any other initialization necessary upon receiving control.

    A task may be started by a Start Task command or a Start SVC. Both methods:

    1. Build the TCB for the task.

    2. Create a TCBTAB entry which points to the task's TCB.

    3. Build the task's initial stack.

    4. Post the task with the initial entry point (INITENT) vector from the task header as the address to receive control when it is first executed.

    When a task initially receives control, it executes at the label designated by the initial entry point (INITENT) vector in its task header.

    The registers have the following initial values:

    
     CS = Initial segment as defined by the task header
    
     IP = Initial offset as defined by the task header
    
     DS = Data segment value from the task header
    
     SS = Stack segment value from the task header
    
     SP = Stack pointer value from the task header
    
          (to word boundary)
    
     ES = Segment of task header
    
     Flags   Interrupt flag    = 1 (enabled)
    
             Carry flag        = 0
    
             Parity            = 0
    
             Sign              = 0
    
             Direction flag    = 0
    
             Trap              = 0
    
             Overflow          = 0
    
             Zero              = 0
    
             Auxiliary carry   = 0
    
    

    AX, BX, CX, DX, SI, DI, and BP are all set to the values defined for the user's stack when the stack area is reserved by the task writer.

    Starting a task does not set the "initialized" bit in its primary status byte; this is done by the Initcomp SVC. After a task has completed initialization, it should use the Initcomp SVC and "wait" itself.

    It is expected that when the task receives control the first time, it will:

    1. Acquire the necessary resources. (This is a recommendation only. In other cases, it may be more appropriate to acquire resources only as they are needed.)

    2. Initialize its BCB.

    3. Does other required initial setup.

    4. Does an Initcomp (initialization complete) SVC, which will mark the task as initialized. The task can receive commands from the system unit. A task that is not initialized may not receive system unit commands. However, the task can be posted, waited, suspended, resumed, interrupted, and request SVCs and other services from the Realtime Control Microcode.

    Permanent Task Status

    A task can mark itself as permanent, via the Initcomp SVC. Permanent classification is determined during the first Initcomp SVC. Further initialization complete SVCs are rejected with a "no-operation" error. If the task needs to be permanent and not receive commands from the system unit, it may set the busy bit in its primary status byte and, after the Initcomp SVC, leave the busy bit set to 1. If a child task requests a permanent status, its parent task is also marked as permanent. No notification is made to the parent task.

    Stopping a Task

    A task that is stopped has no TCBTAB entry, but still has an entry in the TASKTAB. It can no longer be put on the dispatch queue. The task may be restarted by a system unit program or another task. The stopped and loaded states are actually the same state. When a task is stopped, all its acquired resources are relinquished and any child tasks are stopped and unloaded. The initialized bit in the task's primary status byte is reset. If the task has a permanent status, any stop request is rejected.

    Waiting Task

    Whenever a task is idle, it should place itself in an idle or wait state. It is now ready for another task or system unit application to request its services. This request can be made through a Post SVC or POSTI service interrupt, which sets the posted flag (POSTED) in the task's TCB. Before a task attempts to "wait" itself, it should first check the posted flag (POSTED) in its TCB. The posted flag must be cleared to 0 by the task or the wait request is a "no-operation."

    Posting a Task

    Posting a task puts the task on the dispatch queue.

    The task's TCB is modified as follows:

    Following the code that issues the Wait SVC should be the task's POST handler. When the task is dispatched again, it will be given control at the code immediately following the Wait SVC.

    The Post handler should reset the posted flag to 0 so that subsequent waits are not no-operations.

    Post puts a task in the dispatch queue if it was waiting and not suspended.

    Dispatching a Task

    A dispatchable task has been posted on the dispatch queue and will be dispatched to execute when it has the highest dispatchable priority or its turn comes on round robin dispatching.

    A task that is executing is in actual control of the co-processor adapter.

    The task's I/O interrupt handlers are entered via interrupt vectors for the I/O and operate asynchronously to the mainline task code; consequently, interrupt handlers are not dispatched but receive control when the interrupt occurs (assuming interrupts are enabled and not masked).

    Suspending a Task

    Suspending a task unconditionally removes the task from the dispatch queue. The "suspended" flag in the task's state byte in the TCB is set to 1. To take a task out of the suspended state, the task is "resumed" via the Resume SVC or the RESUMEI service interrupt.

    If the suspended task is posted, it is not put on the dispatch queue until it is resumed.

    Resuming a Task

    Resuming a task cancels the suspended state of a task and resets the suspend flag in the task's state byte (in the task's TCB). If the queued flag in the task's state byte (in the task's TCB) is on, resuming a task causes it to be put on the dispatch queue.

    The following figure shows the progression of a typical task through various states:

    
                                  TASK STATE DIAGRAM
    
                                  ------------------
    
         +---+                  +---+                  +---+
    
         | 1 |==> Started       | 2 |==> Suspend       | 3 |==> Resume
    
         +---+                  +---+                  +---+
    
    
    
         +---+                  +---+                  +---+
    
         | 4 |==> Preempt       | 5 |==> Dispatch      | 6 |==> Stayres
    
         +---+                  +---+                  +---+
    
    
    
                                +---+
    
                                |   |==> Defined states
    
                                +---+
    
    
    
    
    
             +------+                                                +---------+
    
      +------+>Wait>+------------------------------------------------+ Loaded, |
    
      |      +------+                  +------+                      | Started,|
    
      |                             +--+<Post<+----------------------+ and     |
    
      |                             |  +------+                      | Waiting |
    
      |                             |                +---------------+-----+-+-+
    
      |                             |                |                     | |
    
      |                             |                |               +---+ | |
    
    +-------------+                 |                |               |>3>+-+ |
    
    | |           |                 |                |               +-+-+   |
    
    | |       +---+--+              |             +--+---+             |     |
    
    | |    +--+<Stop<+----------------------------+<Stop<+-----------+ |   +-+-+
    
    | |    |  +---+--+              |             +--+---+           | | +-+<2<|
    
    | |    |      +-------------+   |                |               | | | +---+
    
    | |    |                    |   |                |               | | |
    
    | |   ++----------+ +---+ +-+---+---+ +---+ +----+----+ +------+ +-+-+-----+
    
    | | +-+Loaded and +-+>1>+-+ Loaded, +-+>2>+-+ Loaded, +-+<Post<+-+ Loaded  |
    
    | | | |not Started| +---+ | Started,| +---+ | Started,| +------+ | Started |
    
    | | | +---------+-+       | and     |       | Posted, |          | Waiting |
    
    | | |           |     +---+ Posted  | +---+ | and     |          | and     |
    
    | | |           +---+ | +-+         +-+<3<+-+Suspended|          |Suspended|
    
    | | |+------------+ | | | +-+------++ +---+ |         +------+   |         |
    
    | | ||>Load,Build>+-+ | |   |      |        +-----+-+++      |   +---+-----+
    
    | | |+-----+------+   | |   |      |  +---+       | ||  +----+-+     |
    
    | | |      |          | | +-+---+  +--+>6>+-----+ | |+--+<Post<|     |
    
    | | |      |          | | |<<5>>+-+   +---+     | | |   +------+     |
    
    | | | +----+---+      | | +-----+ |             | | |                |
    
    | | | |Unloaded+-+    | |         |             | | |                |
    
    | | | +--------+ |    | | +---+   |  +--------+ | | |                |
    
    | | |            |    | +-+<4<+-+ |  |Resident+-+ | |                |
    
    | | | +--------+ |    |   +---+ | |  +--------+ | | |                |
    
    | | +-+>Unload>+-+    |         | |             | | |                |
    
    | |   +----+-+-+      |   +-----+-+-+  +---+    | | |                |
    
    | |        | +--------+   |         +--+>6>+----+ | |                |
    
    | |        |              | Loaded, |  +---+      | |                |
    
    | |        |   +------+   | Started,|             | |                |
    
    | +------------+<Wait<+---+ Posted, |             | |                |
    
    |          |   +------+   | and     | +---------+ | |                |
    
    | +------+ |              |Executing+-+>Suspend>+-+ |                |
    
    +-+<Stop<+----------------+         | +---------+   |                |
    
      +------+ |              +----+----+               |                |
    
               |                   |                    |                |
    
               |              +----+---+          +-----+--+             |
    
               +--------------+<Unload<+----------+<Unload<+-------------+
    
                              +--------+          +--------+
    
    

    Associated Interface Modules

    The following interface modules are related to task management:

    
    ----------------------------------------------------------
    
     Type                      Invocation      Name
    
    ----------------------------------------------------------
    
     SVC                       AH = 38h,       UNLOAD
    
                               INT = 56h
    
    
    
     SVC                       AH = 39h,       BUILD
    
                               INT = 56h
    
    
    
     SVC                       AH = 3Ah,       START
    
                               INT = 56h
    
    
    
     SVC                       AH = 3Bh,       STOP
    
                               INT = 56h
    
    
    
     SVC                       AH = 3Ch,       WAIT
    
                               INT = 56h
    
    
    
     SVC                       AH = 3Dh,       SUSPEND
    
                               INT = 56h
    
    
    
     SVC                       AH = 3Eh,       RESUME
    
                               INT = 56h
    
    
    
     SVC                       AH = 3Fh,       POST
    
                               INT = 56h
    
    
    
     SVC                       AH = 40h,       ASAP
    
                               INT = 56h
    
    
    
     SVC                       AH = 41h,       STAYRES
    
                               INT = 56h
    
    
    
     SVC                       AH = 48h,       INITCOMP
    
                               INT = 56h
    
    
    
     Service Interrupt         INT 64h         POSTI
    
    
    
     Service Interrupt         INT 66h         RESUMEI
    
    

    Resource Blocks

    The Realtime Control Microcode manages the various resources of the co-processor adapter. An application task requests temporary ownership of a resource via SVC 46h "ALLOC" (allocate resource). If the resource is available, the Realtime Control Microcode assigns temporary ownership of it to the task, which must follow certain rules regarding the use of the resource. The task is responsible for returning ownership of the resource to the Realtime Control Microcode via Return SVC 47h deallocate resource).

    Available Resources

    Realtime Interface Co-Processor Adapter resources that may be acquired by application tasks are:

    Realtime Interface Co-Processor Multiport and Realtime Interface Co-Processor Multiport/2 resources which may be acquired by application tasks are:

    Resource Block Definition

    The resource block is used by the application task to request (allocate), temporarily own, and return (deallocate) use of a given co-processor adapter resource. Each request for temporary ownership of a resource requires a resource block.

    Resource blocks must be defined with these considerations:

    User Interface Rules

    Rules for resource management that an application task must follow include:

    Each of the co-processor adapter following resources is discussed separately in the following sections:

    
    ----------------------------------------------------------
    
    Resource                 Block Descriptor
    
                             Value
    
    ----------------------------------------------------------
    
    User-requestable
    
    Interrupt Vectors        01h
    
    
    
    RAM storage              02h
    
    
    
    SCC/CIO port packages    03h
    
    
    
    DMA channels             04h
    
    
    
    User queues              05h
    
    
    
    Hardware timers          06h
    
    
    
    Software timers          07h
    
    
    
    RS-232-C ports           08h
    
    
    
    SCC ports                09h
    
    
    
    CIO ports                0Ah
    
    
    
    RS-422-A ports           0Bh
    
    

    User-Requestable Interrupt Vectors (01h)

    There are 112 allocatable interrupt vectors. The co-processor adapter hardware uses all interrupts below 20h. The Realtime Control Microcode uses all even-numbered vectors 20h-FEh. All odd vectors 21h-FFh are resources to be used by an application task. Certain of these vectors have special meaning. The interrupt vector table assignments are shown under Chapter 11. "Interrupt Vector Table Map for the Realtime Interface Co-Processor, Multiport, and Multiport/2 Adapters".

    A task may request any of the odd interrupt vectors between 21h and 0FFh. The requests are limited only by the storage available for resource blocks in the task header segment. It is permissible to request the same interrupt vector more than once, since each interrupt vector may have multiple owners, provided that a different interrupt vector resource block is used with each request.

    When one of the user-requestable interrupts occurs, the Realtime Control Microcode receives control and, if the vector is owned task, passes control to the last task that requested this interrupt vector. Control is passed by a doubleword jump through the task's resource block.

    After the task has completed processing the interrupt, it should do a doubleword jump through the old vector in its own resource block, which takes it to the next most-recent requestor of this resource or, at completion, to the Realtime Control Microcode's first-level interrupt handler. The least-recent requestor returns control to the Realtime Control Microcode's first-level interrupt handler if each task passes control correctly. The Realtime Control Microcode completes the interrupt handling and returns control to the task that was interrupted.

    The Realtime Control Microcode's first-level interrupt handler requires the use of registers BX, SI, and DS. Those registers may not be used for passing parameters. The Realtime Control Microcode also uses three words of stack space prior to passing control to the first task.

    User-Requestable Interrupt Vector Resource Block

    The resource block (VECRB) for a user-requestable vector is shown in the following diagram:

    Purpose:
    Used to allocate and return user-requestable interrupt vectors

    Location:
    Task header segment in task storage

    Size:
    1Ch bytes per block

    Initialization:
    Initial values set by task
    
    +----------------------------------------------------------------+
    
    
    
    | User-Requestable Interrupt Vector Resource Block               |
    
    
    
    +-------+----------+-----------------------------+---------------+
    
    
    
    | Byte  | Field    | Description                 | Comments      |
    
    |       | Name     |                             |               |
    
    
    
    +-------+----------+-----------------------------+---------------+
    
    | 00h-  | NEXT     | Pointer to next in list;    |               |
    
    | 01h   |          | set by the Realtime Control |               |
    
    |       |          | Microcode.                  |               |
    
    +-------+----------+-----------------------------+---------------+
    
    | 02h-  | PREV     | Pointer to previous block   |               |
    
    | 03h   |          | in list; set by the         |               |
    
    |       |          | Realtime Control Microcode. |               |
    
    +-------+----------+-----------------------------+---------------+
    
    | 04h   | 01h      | Block descriptor.           | = 01h         |
    
    +-------+----------+-----------------------------+---------------+
    
    | 05h   | VECTOR   | Interrupt vector number.    | Must be above |
    
    |       |          |                             | 20h and odd   |
    
    +-------+----------+-----------------------------+---------------+
    
    | 06h   | VECTSK   | Owner task # of this block. |               |
    
    +-------+----------+-----------------------------+---------------+
    
    | 07h   | Reserved | Reserved.                   | Must be 0     |
    
    +-------+----------+-----------------------------+---------------+
    
    | 08h-  | NEWOFF   | Offset for new vector.      |               |
    
    | 09h   |          |                             |               |
    
    +-------+----------+-----------------------------+---------------+
    
    | 0Ah-  | NEWSEG   | Segment for new vector.     |               |
    
    | 0Bh   |          |                             |               |
    
    +-------+----------+-----------------------------+---------------+
    
    | 0Ch-  | OLDVEC   | Old vector offset:          |               |
    
    | 0Fh   |          | segment; set by the         |               |
    
    |       |          | Realtime Control Microcode  |               |
    
    +-------+----------+-----------------------------+---------------+
    
    | 10h-  | QUICKVEC | Quick vector value; set by  |               |
    
    | 13h   |          | the Realtime Control        |               |
    
    |       |          | Microcode.                  |               |
    
    +-------+----------+-----------------------------+---------------+
    
    | 14h-  | Reserved | Set and used by the         |               |
    
    | 1Bh   |          | Realtime Control Microcode  |               |
    
    |       |          | to link other tasks sharing |               |
    
    |       |          | the same interrupt vector.  |               |
    
    +-------+----------+-----------------------------+---------------+
    
    

    User-Requested Interrupt Vector Resource Block Definition

    The task must initialize the following fields in the resource block before the allocation request is made:

    
      01h        Resource block descriptor
    
      VECTOR     Interrupt vector number
    
      VECTSK     Owner task number
    
      NEWOFF     Offset for new vector
    
      NEWSEG     Segment for new vector
    
    

    The Realtime Control Microcode completes the following fields in the resource block following successful allocation of the resource to the application task.

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      OLDVEC     Old vector offset:segment
    
      QUICKVEC   Quick vector value
    
    

    Allocation of User-Requestable Interrupt Vectors

    SVC 46h is used to allocate use of a particular interrupt vector to the requesting application task.

    Ownership of a User-Requestable Interrupt Vector

    Deallocation of User-Requestable Interrupt Vectors

    SVC 47h is used to return or deallocate ownership of the same interrupt vector to the Realtime Control Microcode.

    Associated Interface Modules

    None

    Random Access Memory (RAM) Storage (02h)

    Co-processor adapters can contain 128KB, 256KB, 512KB, or 960KB of base RAM. Blocks of storage may be allocated to application tasks. These blocks are allocated in paragraph (16 byte) multiples, can be requested to start on specified boundaries, and can be allocated from high or low storage.

    RAM Storage Resource Block

    The following diagram defines the RAM storage resource block (STRRB):

    Purpose:
    Used to allocate and return RAM storage blocks

    Location:
    Task header segment in task storage

    Size:
    10h bytes per block

    Initialization:
    Initial values set by task
    
    +-----------------------------------------------------------------+
    
    
    
    | RAM Storage Resource Block                                      |
    
    
    
    +-------+---------+-----------------------------+-----------------+
    
    
    
    | Byte  | Field   | Description                 | Comments        |
    
    |       | Name    |                             |                 |
    
    
    
    +-------+---------+-----------------------------+-----------------+
    
    | 00h-  | NEXT    | Pointer to next block in    |                 |
    
    | 01h   |         | list; set by the            |                 |
    
    |       |         | Realtime Control Microcode. |                 |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 02h-  | PREV    | Pointer to previous block   |                 |
    
    | 03h   |         | in list; set by the         |                 |
    
    |       |         | Realtime Control Microcode. |                 |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 04h   | 02h     | Block descriptor.           | = 02h           |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 05h   | HIGHLOW | High or low storage flag.   | 0 = Low storage |
    
    |       |         |                             | request.        |
    
    |       |         |                             | Non-0 = High    |
    
    |       |         |                             | storage request |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 06h   | STRTSK  | Owner task # of this block. |                 |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 07h   | Reserved| Reserved.                   | Must be 0.      |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 08h-  | STRBND  | Requested storage boundary  | Must be a       |
    
    | 09h   |         | in paragraphs.              | power of 2      |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 0Ah-  | STRSIZE | Storage size of requested   |                 |
    
    | 0Bh   |         | block in paragraphs         |                 |
    
    |       |         | 16-byte increments).        |                 |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 0Ch-  | STRSEG  | Segment of storage block;   |                 |
    
    | 0Dh   |         | set by the Realtime Control |                 |
    
    |       |         | Microcode.                  |                 |
    
    +-------+---------+-----------------------------+-----------------+
    
    | 0Eh-  | PARTIAL | Partial return size in      |                 |
    
    | 0Fh   |         | paragraphs.                 |                 |
    
    +-------+---------+-----------------------------+-----------------+
    
    

    RAM Storage Resource Block Definition

    The task must initialize the following fields in the resource block before the allocation request is made:

    
      02h        Resource block descriptor
    
      HIGHLOW    High/low storage flag
    
      STRTSK     Owner task number
    
      STRBND     Requested storage boundary
    
      STRSIZE    Requested storage size
    
    

    The following fields in the resource block are completed by the Realtime Control Microcode following the allocation request by the task:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      STRSEG     Block segment of storage block
    
      PARTIAL    Partial return size
    
    

    The PARTIAL field is an exception to the rule not to modify a resource block between allocation and deallocation. Refer to "Deallocation of RAM Storage" in this subsection for further details.

    Allocation of RAM Storage

    Ownership of RAM Storage

    If a task owns storage other tasks are using and the owner task is stopped, the storage should not be accessed by the other tasks. For this reason, whenever a parent task is stopped, all of the child tasks of that task are also stopped.

    Deallocation of RAM Storage

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type              Invocation      Name
    
    ----------------------------------------------------------
    
     Diagnostic        AH = 00h,       RAM TEST
    
     test              INT FEh
    
    
    
     Diagnostic        AH = 01h,       CHECKSUM TEST
    
     test              INT FEh
    
    

    SCC/CIO Port Packages (03h)

    The SCC/CIO port packages consist of either SCC Port 0 and CIO Port 0 as a unit or SCC Port 1 and CIO Port 1 as a unit.

    The components consist of the Z8030 Serial Communications Controller (SCC) and the Z8036 Counter/Interface/Output (CIO) chip.

    Parts of the functions of these two devices may be requested as a package. A user requests either or both of the two CIO/SCC port packages (one at a time). For more details regarding the hardware configuration of the SCC and the CIO, refer to the hardware volumes of this manual. For a list of possible resource conflicts, see "Resource Conflicts Table".

    SCC/CIO Port Package Resource Block

    The SCC/CIO Port Package resource block (SCCRB) is defined in the table that follows:

    Purpose:
    Used to allocate and return a SCC/CIO port package

    Location:
    Task header segment in task storage

    Size:
    38h bytes per block

    Initialization:
    Initial values set by task
    
    +--------------------------------------------------------------+
    
    
    
    | SCC/CIO Port Package Resource Block                          |
    
    
    
    +-------+-------------+----------------------------+-----------+
    
    
    
    | Byte  | Field Name  | Description                | Comments  |
    
    
    
    +-------+-------------+----------------------------+-----------+
    
    | 00h-  | NEXT        | Pointer to next block      |           |
    
    | 01h   |             | in list; set by the        |           |
    
    |       |             | Realtime Control Microcode.|           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 02h-  | PREV        | Pointer to previous        |           |
    
    | 03h   |             | block in list; set by the  |           |
    
    |       |             | Realtime Control Microcode.|           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 04h   | 03h         | Block descriptor.          | = 03h     |
    
    +-------+-------------+----------------------------+-----------+
    
    | 05h   | SCCNUM      | SCC/CIO port.              | = 0 - 1   |
    
    +-------+-------------+----------------------------+-----------+
    
    | 06h   | SCCTSK      | Owner task number of this  |           |
    
    |       |             | block.                     |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 07h   | Reserved    | Reserved.                  | Must be 0.|
    
    +-------+-------------+----------------------------+-----------+
    
    | 08h-  | XMITOFF     | Offset to transmit         |           |
    
    | 09h   |             | interrupt vector.          |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 0Ah-  | XMITSEG     | Segment to transmit        |           |
    
    | 0Bh   |             | interrupt vector.          |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 0Ch-  | RECOFF      | Offset to receive          |           |
    
    | 0Dh   |             | interrupt vector for       |           |
    
    |       |             | SCC receive interrupt.     |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 0Eh-  | RECSEG      | Segment to receive         |           |
    
    | 0Fh   |             | interrupt vector.          |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 10h-  | ERROFF      | Offset to error interrupt  | See note  |
    
    | 11h   |             | vector.                    | below.    |
    
    +-------+-------------+----------------------------+-----------+
    
    | 12h-  | ERRSEG      | Segment to error interrupt | See note  |
    
    | 13h   |             | vector.                    | below.    |
    
    +-------+-------------+----------------------------+-----------+
    
    | 14h-  | EXTOFF      | Offset to external         |           |
    
    | 15h   |             | interrupt vector.          |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 16h-  | EXTSEG      | Segment to external        |           |
    
    | 17h   |             | interrupt vector.          |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 18h-  | CIOOFF      | CIO bit 0 interrupt        |           |
    
    | 19h   |             | vector offset.             |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 1Ah-  | CIO0SEG     | CIO bit 0 interrupt        |           |
    
    | 1Bh   |             | vector segment.            |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 1Ch-  | CIO1OFF     | CIO bit 1 interrupt        |           |
    
    | 1Dh   |             | vector offset.             |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 1Eh-  | CIO1SEG     | CIO bit 1 interrupt        |           |
    
    | 1Fh   |             | vector segment.            |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 20h-  | CIO2OFF     | CIO bit 2 interrupt        |           |
    
    | 21h   |             | vector offset.             |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 22h-  | CIO2SEG     | CIO bit 2 interrupt        |           |
    
    | 23h   |             | vector segment.            |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 24h-  | CIO3OFF     | CIO bit 3 interrupt        |           |
    
    | 25h   |             | vector offset.             |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 26h-  | CIO3SEG     | CIO bit 3 interrupt        |           |
    
    | 27h   |             | vector segment.            |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 28h-  | CIO4OFF     | CIO bit 4 interrupt        |           |
    
    | 29h   |             | vector offset.             |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 2Ah-  | CIO4SEG     | CIO bit 4 interrupt        |           |
    
    | 2Bh   |             | vector segment.            |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 2Ch-  | CIO5OFF     | CIO bit 5 interrupt        |           |
    
    | 2Dh   |             | vector offset.             |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 2Eh-  | CIO5SEG     | CIO bit 5 interrupt        |           |
    
    | 2Fh   |             | vector segment.            |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 30h-  | CIO6OFF     | CIO bit 6 interrupt        |           |
    
    | 31h   |             | vector offset.             |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 32h-  | CIO6SEG     | CIO bit 6 interrupt        |           |
    
    | 33h   |             | vector segment.            |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 34h-  | SCCBAS      | SCC base register          |           |
    
    | 35h   |             | address.  Set by the       |           |
    
    |       |             | Realtime Control           |           |
    
    |       |             | Microcode.                 |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 36h-  | CIOBAS      | CIO base register          |           |
    
    | 37h   |             | address.  Set by the       |           |
    
    |       |             | Realtime Control           |           |
    
    |       |             | Microcode.                 |           |
    
    +-------+-------------+----------------------------+-----------+
    
    

    Note:

    The error interrupt is equivalent to the Zilog SCC special receive condition interrupt.

    SCC/CIO Port Package Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      03h        Resource block descriptor
    
      SCCTSK     Owner task number
    
      SCCNUM     SCC/CIO port number (0 or 1 only)
    
      xxxOFF     Requested Interrupt vector offset (dependent
    
                 on type of service)
    
      xxxSEG     Requested interrupt vector segment
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      SCCBAS     SCC base address
    
      CIOBAS     CIO register address
    
    

    Allocation of SCC/CIO Port Packages

    Ownership of SCC/CIO Port Packages

    Deallocation of SCC/CIO Port Packages

    SVC 47h is used to return ownership of the particular SCC/CIO port package to the control of the Realtime Control Microcode.

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    INT A2h         SCCRESET
    
    
    
     PROM Service    INT A4h         SCCREGS
    
    
    
     PROM Service    INT A6h         CIOREGS
    
    
    
     Diagnostic      AH = 08h,       CONFIGURE
    
     test            INT = FEh       CIO PORT
    
    
    
     Diagnostic      AH = 09h,       CONFIGURE
    
     test            INT = FEh       SCC CHANNEL
    
    
    
     Service         AH = 00h,       Half Rate Select
    
     Interrupt       INT = 74h       Control
    
    
    
     Service         AH = 01h,       Transmit Control
    
     Interrupt       INT = 74h
    
    
    
     Service         AH = 02h,       RTS/DTR Control
    
     Interrupt       INT = 74h
    
    
    
     Service         AH = 03h,       Query External/Status
    
     Interrupt       INT = 74h       Inputs
    
    
    
     Service         AH = 06h,       Read/Write CIO Bits
    
     Interrupt       INT = 74h
    
    

    DMA Channels (04h)

    There are two DMA channels located on the co-processor adapter. A task may request either or both (one at a time) of the two DMA channels. These channels are part of the 80186 processor and can be connected to either of the SCC/CIO port packages, SCC ports 0 and 1, RS-232-C ports 0 and 1, or RS-422-A ports 0 and 1. PROM Services routines aid a task in establishing these linkages and configuring the DMA channel.

    DMA Channel Resource Block

    The following diagram defines the DMA Channel Resource Block (DMARB):

    Purpose:
    Used to allocate and return a DMA Channel

    Location:
    Task header segment of task storage

    Size:
    0Eh bytes per block

    Initialization:
    Initial values set by task
    
    +--------------------------------------------------------------+
    
    
    
    | DMA Channel Resource Block                                   |
    
    
    
    +-------+-------------+----------------------------+-----------+
    
    
    
    | Byte  | Field Name  | Description                | Comments  |
    
    
    
    +-------+-------------+----------------------------+-----------+
    
    | 00h-  | NEXT        | Pointer to next block in   |           |
    
    | 01h   |             | list; set by the Realtime  |           |
    
    |       |             | Control Microcode.         |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 02h-  | PREV        | Pointer to previous        |           |
    
    | 03h   |             | block in list; set         |           |
    
    |       |             | by the Realtime            |           |
    
    |       |             | Control Microcode.         |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 04h   | 04h         | Block descriptor.          | = 04h     |
    
    +-------+-------------+----------------------------+-----------+
    
    | 05h   | DMANUM      | DMA channel number.        | = 0 or 1  |
    
    +-------+-------------+----------------------------+-----------+
    
    | 06h   | DMATSK      | Owner task number of this  |           |
    
    |       |             | block.                     |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 07h   | Reserved    | Reserved.                  | Must be 0 |
    
    +-------+-------------+----------------------------+-----------+
    
    | 08h-  | DMAOFF      | Offset to interrupt vector |           |
    
    | 09h   |             | for DMA terminal count.    |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 0Ah-  | DMASEG      | Segment to DMA terminal    |           |
    
    | 0Bh   |             | count interrupt vector.    |           |
    
    +-------+-------------+----------------------------+-----------+
    
    | 0Ch-  | DMABASE     | DMA base address; set      |           |
    
    | 0Dh   |             | by the Realtime Control    |           |
    
    |       |             | Microcode.                 |           |
    
    |       |             |                            |           |
    
    +-------+-------------+----------------------------+-----------+
    
    

    DMA Channel Resource Block Definition

    It is the task's responsibility to define the following fields in the resource block before the allocation request is made:

    
      04h        Resource Block descriptor
    
      DMANUM     DMA channel number
    
      DMATSK     Owner task number
    
      DMAOFF     Offset to interrupt vector for DMA terminal count
    
      DMASEG     Segment to interrupt vector
    
    

    The Realtime Control Microcode completes the following fields in the resource block when the allocation call is completed successfully:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      DMABASE    DMA base address
    
    

    Allocation of DMA Channels

    Ownership of DMA Channels

    No special rules apply to the use of DMA channel resources except those general rules outlined under "Resource Blocks".

    Interrupt Handling

    Deallocation of DMA Channels

    SVC 47h is invoked by the application task to release ownership of DMA channels. For details, see Volume 2, Chapter 5 "Supervisor Calls".

    Associated Interface Modules

    
    ----------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------
    
     PROM Service    INT AAh         DMACONNECT
    
    
    
     PROM Service    INT ACh         DMASUPPORT
    
    
    
     PROM Service    INT AEh         DMAREGS
    
    
    
     PROM Service    INT B0h         DMASTOP
    
    
    
     PROM Service    INT B2h         DMAADDR
    
    
    
     Diagnostic      AH = 0Ah,       CONFIGURE
    
     Test            INT = FEh       DMA CHANNEL
    
    

    User Queues (05h)

    The user queue is the basic method of intertask communication. There may be up to 255 user queues. The maximum number of user queues assigned to a co-processor adapter is controlled by MAXQUEUE defined in the ICAPARM.PRM file. This value resides at 0446h in the interface block. The maximum number of user queues that a task may request is MAXQUEUE+1. The actual queue bodies are called "user queue elements" and reside in the user task's storage area.

    User Queue Resource Block

    The following diagram defines the User Queue Resource Block (QEURB):

    Purpose:
    Used to allocate and return user queues

    Location:
    Task header segment in task storage

    Size:
    08h bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------+
    
    
    
    | User Queue Resource Block                                     |
    
    
    
    +-------+---------+----------------------------+----------------+
    
    
    
    | Byte  | Field   | Description                | Comments       |
    
    |       | Name    |                            |                |
    
    
    
    +-------+---------+----------------------------+----------------+
    
    | 00h-  | NEXT    | Pointer to next block in   |                |
    
    | 01h   |         | list; set by the Realtime  |                |
    
    |       |         | Control Microcode.         |                |
    
    +-------+---------+----------------------------+----------------+
    
    | 02h-  | PREV    | Pointer to previous block  |                |
    
    | 03h   |         | in list; set by the        |                |
    
    |       |         | Realtime Control Microcode.|                |
    
    +-------+---------+----------------------------+----------------+
    
    | 04h   | 05h     | Block descriptor.          | = 05h          |
    
    +-------+---------+----------------------------+----------------+
    
    | 05h   | QUENUM  | User queue number.         | = 0h - MAXQUEUE|
    
    +-------+---------+----------------------------+----------------+
    
    | 06h   | QUETSK  | Owner task number of this  |                |
    
    |       |         | block.                     |                |
    
    +-------+---------+----------------------------+----------------+
    
    | 07h   | Reserved| Reserved                   | Must be 0      |
    
    +-------+---------+----------------------------+----------------+
    
    

    User Queue Resource Block Definition

    The task must complete the following fields in the resource block prior to the allocation request:

    
      05h        Resource Block descriptor
    
      QUENUM     Queue number
    
      QUETSK     Owner task number
    
    

    The Realtime Control Microcode, upon allocation, completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
    

    Allocation of User Queues

    Temporary ownership of one or more user queues is obtained via SVC 46h. For details, see Volume 2, Chapter 5 "Supervisor Calls".

    Ownership of User Queues

    Purpose:
    Used by tasks for communication and storage buffers

    Location:
    Task storage or acquired storage

    Size:
    Task defined

    Initialization:
    Initial values are task-defined
    
    +------------------------------------------------------------------+
    
    
    
    | User Queue Element                                               |
    
    
    
    +-------+-------------+----------------------------+---------------+
    
    
    
    | Byte  | Field Name  | Description                | Comments      |
    
    
    
    +-------+-------------+----------------------------+---------------+
    
    | 00h-  | Offset of   | Offset to next user queue  |               |
    
    | 01h   | next        | element.  Set by the       |               |
    
    |       | element     | Realtime Control Microcode.|               |
    
    +-------+-------------+----------------------------+---------------+
    
    | 02h-  | Segment of  | Segment of next user       | = 0 indicates |
    
    | 03h   | next        | queue element.  Set by     | this is last  |
    
    |       | element     | Realtime Control Microcode.| element       |
    
    +-------+-------------+----------------------------+---------------+
    
    | 04h   |                                                          |
    
    +-------+                                                          |
    
    |  .    |                                                          |
    
    |  .    |                                                          |
    
    |  .    |                                                          |
    
    |  .    |                                                          |
    
    +-------+       User-defined data for user-defined length.         |
    
    |  .    |                                                          |
    
    |  .    |                                                          |
    
    |  .    |                                                          |
    
    |  .    |                                                          |
    
    +-------+                                                          |
    
    | nh    |                                                          |
    
    +-------+----------------------------------------------------------+
    
    

    Deallocation of User Queues

    Release of a user queue is performed via the SVC 47h.

    Associated Interface Modules

    
    -------------------------------------------
    
     Type            Invocation      Name
    
    -------------------------------------------
    
     Service         INT 6Ah         RECQUEUE
    
     Interrupt
    
    
    
     Service         INT 6Ch         ADDQUEUE
    
     Interrupt
    
    
    
     Service         INT 6Eh         REMQUEUE
    
     Interrupt
    
    

    Hardware Timers (06h)

    Two hardware timers are located on the Realtime Interface Co-processor and five hardware timers on the Realtime Interface Co-Processor Multiport or Realtime Interface Co-Processor Multiport/2 available for use by application tasks. The hardware timers have a granularity of 543 nanoseconds, providing a delay range from 543 nanoseconds to 35 milliseconds. These timers are used by tasks with precise timing requirements. If a task's timing requirements are satisfied by minimum time outs in multiples of 5 milliseconds, it is more appropriate for the task to acquire a software timer. Software timers are described in detail in the next subsection in this chapter. For example, a task that wants to report an error if an event does not occur within 100 milliseconds should use a software timer since the error still exists if the task is not notified until 101 milliseconds. However, if a task wants to perform an event precisely every 3 milliseconds, a CIO hardware timer is required.

    Hardware Timer Resource Block

    The format of the Hardware Timer Resource Block (HTIMRB) is shown in the table that follows:

    Purpose:
    Used to allocate and return one of the CIO hardware timers

    Location:
    Task header segment in task storage

    Size:
    0Eh bytes per block

    Initialization:
    Initial values set by task
    
    +------------------------------------------------------------+
    
    
    
    | Hardware Timer Resource Block                              |
    
    
    
    +------+------------+----------------------------+-----------+
    
    
    
    | Byte | Field Name | Description                | Comments  |
    
    
    
    +------+------------+----------------------------+-----------+
    
    | 00h- | NEXT       | Pointer to next block in   |           |
    
    | 01h  |            | list; set by Realtime      |           |
    
    |      |            | Control Microcode.         |           |
    
    +------+------------+----------------------------+-----------+
    
    | 02h- | PREV       | Pointer to previous block  |           |
    
    | 03h  |            | in list; set by Realtime   |           |
    
    |      |            | Control Microcode.         |           |
    
    +------+------------+----------------------------+-----------+
    
    | 04h  |  06h       | Block descriptor.          | = 06h     |
    
    +------+------------+----------------------------+-----------+
    
    | 05h  | HTIMNUM    | Hardware timer port number.|           |
    
    |      |            | Variable, depending on the |           |
    
    |      |            | co-processor adapter.      |           |
    
    +------+------------+----------------------------+-----------+
    
    | 06h  | HTIMTSK    | Owner task number of this  |           |
    
    |      |            | block.                     |           |
    
    +------+------------+----------------------------+-----------+
    
    | 07h  | Reserved   | Reserved.                  | Must be 0 |
    
    +------+------------+----------------------------+-----------+
    
    | 08h- | HTIMOFF    | Interrupt vector offset    |           |
    
    | 09h  |            | for hardware timer         |           |
    
    |      |            | interrupt.                 |           |
    
    +------+------------+----------------------------+-----------+
    
    | 0Ah- | HTIMSEG    | Interrupt vector segment   |           |
    
    | 0Bh  |            | for hardware timer         |           |
    
    |      |            | interrupt.                 |           |
    
    +------+------------+----------------------------+-----------+
    
    | 0Ch- | HTIMBAS    | Base I/O address of timer. |           |
    
    | 0Dh  |            |                            |           |
    
    +------+------------+----------------------------+-----------+
    
    

    Hardware Timer Resource Block Definition

    The application task must complete the following fields in the resource block before the allocation request is made:

    
      06h        Resource Block descriptor
    
      HTIMNUM    Hardware timer number
    
      HTIMTSK    Owner task number
    
      HTIMOFF    Offset address to timer interrupt handler vector
    
      HTIMSEG    Segment address to timer interrupt handler
    
                 vector
    
    

    The Realtime Control Microcode completes the following fields in the resource block when allocation of ownership is made:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      HTIMBAS    Base I/O address of timer
    
    

    Allocation of Hardware Timers

    Allocation of a hardware timer to an application is performed through a call to SVC 46h.

    Ownership of Hardware Timers

    Deallocation of Hardware Timers

    Associated Interface Modules

    
    ---------------------------------------------
    
     Type            Invocation      Name
    
    ---------------------------------------------
    
     PROM Service    INT A8h         CIOTMR
    
    
    
     Diagnostic      AH = 0Bh,       CONFIGURE
    
     test            INT = FEh       HARDWARE
    
                                     TIMER
    
    

    Software Timers (07h)

    There are up to 255 software timers. The actual number of software timers assigned to a co-processor adapter is the value of MAXTIME +1 at offset 0447h in the interface block. MAXTIME is originally defined in the ICAPARM.PRM file.

    Timers are either "single shot" (one-shot) timers or periodic timers. The increment value of a software timer is 5 milliseconds. The range is 5 milliseconds to 327.675 seconds. CPU timer 0 is used for the software timers. Software timers are used to notify a task that a minimum of the requested time out has occurred. These time outs are reasonably accurate, but the task should not depend on them for exact timing measurements. Timeout requests for the software timers are made for the number of 5 millisecond intervals that the task needs. A task requesting a time out of 3 is notified after 15 milliseconds; a task requesting a time out of 10 is notified after 50 milliseconds.

    Software Timer Resource Block

    The format of the Software Timer Resource Block (STIMRB) is shown in the table that follows:

    Purpose:
    Used to allocate and return one of the software timers

    Location:
    Task header segment in task storage

    Size:
    08h bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------+
    
    
    
    | Software Timer Resource Block                                 |
    
    
    
    +------+------------+---------------------------+---------------+
    
    
    
    | Byte | Field Name | Description               | Comments      |
    
    
    
    +------+------------+---------------------------+---------------+
    
    | 00h- | NEXT       | Pointer to next block in  |               |
    
    | 01h  |            | list; set by Realtime     |               |
    
    |      |            | Control Microcode.        |               |
    
    +------+------------+---------------------------+---------------+
    
    | 02h- | PREV       | Pointer to previous block |               |
    
    | 03h  |            | in list; set by Realtime  |               |
    
    |      |            | Control Microcode.        |               |
    
    +------+------------+---------------------------+---------------+
    
    | 04h  | 07h        | Block descriptor.         | = 07h         |
    
    +------+------------+---------------------------+---------------+
    
    | 05h  | STIMNUM    | Software timer number.    | = 0 to MAXTIME|
    
    +------+------------+---------------------------+---------------+
    
    | 06h  | STIMTSK    | Owner task number of this |               |
    
    |      |            | block.                    |               |
    
    +------+------------+---------------------------+---------------+
    
    | 07h  | Reserved   | Reserved.                 | Must be 0     |
    
    +------+------------+---------------------------+---------------+
    
    

    Software Timer Resource Block Definition

    Upon request for allocation of a software timer, the application task should have completed the following fields in the resource block:

    
      07h        Resource Block descriptor
    
      STIMNUM    Software timer number
    
      STIMTSK    Owner task number
    
    

    The Realtime Control Microcode completes the following fields in the resource block after allocation is performed:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
    

    None of these fields should be altered between allocation and return.

    Allocation of Software Timers

    Temporary ownership of a software timer is obtained through a call to SVC 46h.

    Ownership of Software Timers

    Deallocation of Software Timers

    Release of software timers is accomplished via a call to SVC 47h.

    Associated Interface Modules

    
    ------------------------------------------
    
     Type            Invocation      Name
    
    ------------------------------------------
    
     SVC             AH = 43h,       TIMERP
    
                     INT = 56h
    
    
    
     SVC             AH = 44h,       TIMER
    
                     INT = 56h
    
    
    
     SVC             AH = 45h,       CANCEL
    
                     INT = 56h
    
    
    
     Service         INT 68h         CANCELI
    
     Interrupt
    
    

    RS-232-C Ports (08h)

    The RS-232-C resource consists of one SCC port with the necessary RS-232-C CIO control lines. An entire CIO port is not included with an RS-232-C port resource. The RS-232-C port is the recommended resource when the use of an SCC port with control lines is required and the electrical interface for the port is RS-232-C.

    The RS-232-C ports may be numbered 0-7, depending on the co-processor adapter and interface boards installed. It is the responsibility of the application to verify that the interface board is appropriate for the resource requested.

    RS-232-C Port Resource Block

    The RS-232-C Port Resource Block (RS2RB) is defined in the table that follows:

    Purpose:
    Used to allocate and return an RS-232-C Port

    Location:
    Task header segment in task storage

    Size:
    1Ah bytes per block

    Initialization:
    Initial values set by task
    
    +--------------------------------------------------------------+
    
    
    
    | RS-232-C Port Resource Block                                 |
    
    
    
    +-------+---------+-----------------------+--------------------+
    
    
    
    | Byte  | Field   | Description           | Comments           |
    
    |       | Name    |                       |                    |
    
    
    
    +-------+---------+-----------------------+--------------------+
    
    | 00h-  | NEXT    | Pointer to next block | Set by the         |
    
    | 01h   |         | in list.              | Realtime Control   |
    
    |       |         |                       | Microcode.         |
    
    +-------+---------+-----------------------+--------------------+
    
    | 02h-  | PREV    | Pointer to previous   | Set by the         |
    
    | 03h   |         | resource block.       | Realtime Control   |
    
    |       |         |                       | Microcode.         |
    
    +-------+---------+-----------------------+--------------------+
    
    | 04h   | 08h     | Block descriptor.     | = 08h              |
    
    +-------+---------+-----------------------+--------------------+
    
    | 05h   | RS2NUM  | RS-232-C port number. | Dependent on the   |
    
    |       |         |                       | co-processor       |
    
    |       |         |                       | adapter and the    |
    
    |       |         |                       | interface boards   |
    
    |       |         |                       | installed.         |
    
    +-------+---------+-----------------------+--------------------+
    
    | 06h   | RS2TSK  | Owner task number.    |                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 07h   | RESERVED| Reserved.             | Must be 0.         |
    
    +-------+---------+-----------------------+--------------------+
    
    | 08h-  | XMITOFF | SCC transmit interrupt|                    |
    
    | 09h   |         | vector.               |                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 0Ah-  | XMITSEG | Segment to transmit   |                    |
    
    | 0Bh   |         | interrupt vector.     |                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 0Ch-  | RECOFF  | Offset to receive     |                    |
    
    | 0Dh   |         | interrupt vector for  |                    |
    
    |       |         | SCC receive interrupt.|                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 0Eh-  | RECSEG  | Segment to receive    |                    |
    
    | 0Fh   |         | interrupt vector.     |                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 10h-  | ERROFF  | Offset to error       |                    |
    
    | 11h   |         | interrupt vector.     |                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 12h-  | ERRSEG  | Segment to error      |                    |
    
    | 13h   |         | interrupt vector.     |                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 14h-  | EXTOFF  | Offset to external    |                    |
    
    | 15h   |         | interrupt vector.     |                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 16h-  | EXTSEG  | Segment to external   |                    |
    
    | 17h   |         | interrupt vector.     |                    |
    
    +-------+---------+-----------------------+--------------------+
    
    | 18h-  | SCCBAS  | SCC base register     | Set by the         |
    
    | 19h   |         | address.              | Realtime Control   |
    
    |       |         |                       | Microcode.         |
    
    +-------+---------+-----------------------+--------------------+
    
    

    RS-232-C Port Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      08h        Resource block descriptor
    
      RS2TSK     Owner task number
    
      RS2NUM     RS-232-C port number
    
      xxxOFF     Requested Interrupt vector offset (dependent on
    
                 type of service)
    
      xxxSEG     Requested interrupt vector segment
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      SCCBAS     SCC base address
    
    

    Allocation of RS-232-C Ports

    Ownership of RS-232-C Ports

    Deallocation of RS-232-C Ports

    SVC 47h is used to return ownership of the particular RS-232-C port to the control of the Realtime Control Microcode.

    Associated Interface Modules

    
    -------------------------------------------------
    
     Type            Invocation      Name
    
    -------------------------------------------------
    
     PROM Service    INT A2h         SCCRESET
    
    
    
     PROM Service    INT A4h         SCCREGS
    
    
    
     PROM Service    INT A6h         CIOREGS
    
    
    
     Diagnostic      AH = 08h,       CONFIGURE
    
     test            INT = FEh       CIO PORT
    
    
    
     Diagnostic      AH = 09h,       CONFIGURE
    
     test            INT = FEh       SCC CHANNEL
    
    
    
     Service         AH = 00h,       Half Rate Select
    
     Interrupt       INT = 74h       Control
    
    
    
     Service         AH = 01h,       Transmit Control
    
     Interrupt       INT = 74h
    
    
    
     Service         AH = 04h,       RTS/DTR Control
    
     Interrupt       INT = 74h
    
    
    
     Service         AH = 03h,       Query External/Status
    
     Interrupt       INT = 74h       Inputs
    
    

    SCC Ports (09h)

    The SCC port resource consists of one SCC port with no associated CIO control lines. This resource type should be allocated only when the SCC/CIO package and RS-232-C and RS-422-A resource types are too restrictive. This resource type is provided to allow dedicated software systems or communication subsystems access to the primitive hardware resource. Valid SCC ports are 0-1 on a Realtime Interface Co-Processor and 0-3 or 0-7 on a Realtime Interface Co-Processor Multiport, or Realtime Interface Co-Processor Multiport/2.

    SCC Port Resource Block

    The SCC Port Resource Block (SCCPRB) is defined in the table that follows:

    Purpose:
    Used to allocate and return a SCC port

    Location:
    Task header segment in task storage

    Size:
    1Ah bytes per block

    Initialization:
    Initial values set by task
    
    +--------------------------------------------------------------+
    
    
    
    | SCC Port Resource Block                                      |
    
    
    
    +-------+-------------+---------------------+------------------+
    
    
    
    | Byte  | Field Name  | Description         | Comments         |
    
    
    
    +-------+-------------+---------------------+------------------+
    
    | 00h-  | NEXT        | Pointer to next     | Set by the       |
    
    | 01h   |             | resource block.     | Realtime Control |
    
    |       |             |                     | Microcode.       |
    
    +-------+-------------+---------------------+------------------+
    
    | 02h-  | PREV        | Pointer to previous | Set by the       |
    
    | 03h   |             | resource block.     | Realtime Control.|
    
    +-------+-------------+---------------------+------------------+
    
    | 04h   | 09h         | Block descriptor.   | = 09h            |
    
    +-------+-------------+---------------------+------------------+
    
    | 05h   | SCCNUM      | SCC port number.    | Dependent on the |
    
    |       |             |                     | co-processor     |
    
    |       |             |                     | adapter and the  |
    
    |       |             |                     | interface boards |
    
    |       |             |                     | installed.       |
    
    +-------+-------------+---------------------+------------------+
    
    | 06h   | SCCTSK      | Owner task number.  |                  |
    
    +-------+-------------+---------------------+------------------+
    
    | 07h   | RESERVED    | Reserved.           | Must be 0.       |
    
    +-------+-------------+---------------------+------------------+
    
    | 08h-  | XMITOFF     | SCC transmit        |                  |
    
    | 09h   |             | interrupt vector.   |                  |
    
    +-------+-------------+---------------------+------------------+
    
    | 0Ah-  | XMITSEG     | Segment to transmit |                  |
    
    | 0Bh   |             | interrupt vector.   |                  |
    
    +-------+-------------+---------------------+------------------+
    
    | 0Ch-  | RECOFF      | Offset to receive   |                  |
    
    | 0Dh   |             | interrupt vector    |                  |
    
    |       |             | for SCC receive     |                  |
    
    |       |             | interrupt.          |                  |
    
    +-------+-------------+---------------------+------------------+
    
    | 0Eh-  | RECSEG      | Segment to receive  |                  |
    
    | 0Fh   |             | interrupt vector.   |                  |
    
    +-------+-------------+---------------------=------------------+
    
    | 10h-  | ERROFF      | Offset to error     | See note below.  |
    
    | 11h   |             | interrupt vector.   |                  |
    
    +-------+-------------+---------------------+------------------+
    
    | 12h-  | ERRSEG      | Segment to error    | See note below.  |
    
    | 13h   |             | interrupt vector.   |                  |
    
    +-------+-------------+---------------------+------------------+
    
    | 14h-  | EXTOFF      | Offset to external  |                  |
    
    | 15h   |             | interrupt vector.   |                  |
    
    +-------+-------------+---------------------+------------------+
    
    | 16h-  | EXTSEG      | Segment to external |                  |
    
    | 17h   |             | interrupt vector.   |                  |
    
    +-------+-------------+---------------------+------------------+
    
    | 18h-  | SCCBAS      | SCC base register   | Set by the       |
    
    | 19h   |             | address.            | Realtime Control |
    
    |       |             |                     | Microcode.       |
    
    +-------+-------------+---------------------+------------------+
    
    

    Note:

    The error interrupt is equivalent to the Zilog SCC special receive condition interrupt.

    SCC Port Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      09h        Resource block descriptor
    
      SCCTSK     Owner task number
    
      SCCNUM     SCC port number
    
      xxxOFF     Requested Interrupt vector offset (dependent
    
                 on type of service)
    
      xxxSEG     Requested interrupt vector segment
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      SCCBAS     SCC base address
    
    

    Allocation of SCC Ports

    Ownership of SCC Ports

    Deallocation of SCC Ports

    SVC 47h is used to return ownership of the particular SCC port to the control of the Realtime Control Microcode.

    Associated Interface Modules

    
    -------------------------------------------------
    
     Type            Invocation      Name
    
    -------------------------------------------------
    
     PROM Service    INT A2h         SCCRESET
    
    
    
     PROM Service    INT A4h         SCCREGS
    
    
    
     Diagnostic      AH = 09h,       CONFIGURE
    
     Test            INT = FEh       SCC CHANNEL
    
    
    
    
    
    

    CIO Ports (0Ah)

    The CIO port resource consists of one CIO port. This resource should be allocated only when the SCC/CIO package, RS-232-C, and RS-422-A resource types are too restrictive. An example of this is where the CIO port definitions have been modified to support a custom interface board. This resource type is provided to allow dedicated software systems or communications subsystems access to the primitive hardware resource. Valid CIO ports are 0-1 on a Realtime Interface Co-Processor and 0-3 on a Realtime Interface Co-Processor Multiport or Realtime Interface Co-Processor Multiport/2.

    CIO Port Resource Block

    The CIO Port Resource Block (CIORB) is defined in the table that follows:

    Purpose:
    Used to allocate and return a CIO port

    Location:
    Task header segment in task storage

    Size:
    0Eh bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------+
    
    
    
    | CIO Port Resource Block                                       |
    
    
    
    +------+-------------+--------------------+---------------------+
    
    
    
    | Byte | Field Name  | Description        |  Comments           |
    
    
    
    +------+-------------+--------------------+---------------------+
    
    | 00h- | NEXT        | Pointer to next    | Set by the Realtime |
    
    | 01h  |             | resource block.    | Control Microcode.  |
    
    +------+-------------+--------------------+---------------------+
    
    | 02h- | PREV        | Pointer to previous| Set by the Realtime |
    
    | 03h  |             | resource block.    | Control Microcode.  |
    
    +------+-------------+--------------------+---------------------+
    
    | 04h  | 0Ah         | Block descriptor.  | = 0Ah               |
    
    +------+-------------+--------------------+---------------------+
    
    | 05h  | CIONUM      | CIO port number.   | Dependent on        |
    
    |      |             |                    | co-processor adapter|
    
    |      |             |                    | (see note).         |
    
    +------+-------------+--------------------+---------------------+
    
    | 06h  | CIOTSK      | Owner task number. |                     |
    
    +------+-------------+--------------------+---------------------+
    
    | 07h  | RESERVED    | Reserved.          | Must be 0.          |
    
    +------+-------------+--------------------+---------------------+
    
    | 08h- | CIOOFF      | CIO interrupt      | Offset              |
    
    | 09h  |             | vector offset.     |                     |
    
    +------+-------------+--------------------+---------------------+
    
    | 0Ah- | CIOSEG      | CIO interrupt      | Segment             |
    
    | 0Bh  |             | vector segment.    |                     |
    
    +------+-------------+--------------------+---------------------+
    
    | 0Ch- | CIOBAS      | CIO base register  | Set by the Realtime |
    
    | 0Dh  |             | address.           | Control Microcode.  |
    
    +------+-------------+--------------------+---------------------+
    
    

    Note:

    See the "Entry Parameters" heading under the , for a discussion on CIO port numbering.

    CIO Port Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      0Ah        Resource Block descriptor
    
      CIONUM     CIO port number
    
      CIOOFF     Requested Interrupt vector offset (dependent
    
                 on type of service)
    
      CIOSEG     Requested interrupt vector segment
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      CIOBAS     CIO register address
    
    

    Allocation of CIO Ports

    Ownership of CIO Ports

    Deallocation of CIO Ports

    SVC 47h is used to return ownership of the particular CIO port to the control of the Realtime Control Microcode.

    Associated Interface Modules

    
    -------------------------------------------------
    
     Type            Invocation      Name
    
    -------------------------------------------------
    
     PROM Service    INT A6h         CIOREGS
    
    
    
     Diagnostic      AH = 08h,       CONFIGURE
    
     test            INT = FEh       CIO PORT
    
    
    
     Service         AH = 06h,       READ/WRITE
    
     Interrupt       INT = 74h       CIO BITS
    
    

    RS-422-A Ports (0Bh)

    The RS-422-A resource consists of one SCC port with the necessary RS-422-A control lines. An entire CIO port is not included with an RS-422-A resource. The RS-422-A port is the recommended resource when the use of a SCC port with the necessary RS-422-A control lines is required and the electrical interface is RS-422-A.

    The RS-422-A ports may be numbered 0-7, depending on the co-processor adapter and the interface boards installed. It is the responsibility of the application to verify that the interface board is appropriate for the resource requested.

    For a list of possible resource conflicts, see "Resource Conflicts Table".

    RS-422-A Port Resource Block

    The RS-422-A Port Resource Block (RS4RB) is defined in the table that follows:

    Purpose:
    Used to allocate and return a RS-422-A Port

    Location:
    Task header segment in task storage

    Size:
    1Ah bytes per block

    Initialization:
    Initial values set by task
    
    +--------------------------------------------------------------+
    
    
    
    | RS-422-A Port Resource Block                                 |
    
    
    
    +-------+------------+-----------------------------+-----------+
    
    
    
    | Byte  | Field Name | Description                 | Comments  |
    
    
    
    +-------+------------+-----------------------------+-----------+
    
    | 00h-  | NEXT       | Pointer to next resource    |           |
    
    | 01h   |            | block; set by Realtime      |           |
    
    |       |            | Control Microcode.          |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 02h-  | PREV       | Pointer to previous         |           |
    
    | 03h   |            | resource block; set by      |           |
    
    |       |            | Realtime Control Microcode. |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 04h   | 0Bh        | Block descriptor.           | = 0Bh     |
    
    +-------+------------+-----------------------------+-----------+
    
    | 05h   | RS4NUM     | RS-422-A port number;       |           |
    
    |       |            | dependent on co-processor   |           |
    
    |       |            | adapter and the interface   |           |
    
    |       |            | boards installed.           |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 06h   | RS4TSK     | Owner task number.          |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 07h   | Reserved   | Reserved.                   | Must be 0.|
    
    +-------+------------+-----------------------------+-----------+
    
    | 08h-  | XMITOFF    | SCC transmit interrupt      |           |
    
    | 09h   |            | vector.                     |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 0Ah-  | XMITSEG    | Segment to transmit         |           |
    
    | 0Bh   |            | interrupt vector.           |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 0Ch-  | RECOFF     | Offset to receive           |           |
    
    | 0Dh   |            | interrupt vector for        |           |
    
    |       |            | SCC receive interrupt.      |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 0Eh-  | RECSEG     | Segment to receive          |           |
    
    | 0Fh   |            | interrupt vector.           |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 10h-  | ERROFF     | Offset to error             | See note  |
    
    | 11h   |            | interrupt vector.           | below.    |
    
    +-------+------------+-----------------------------+-----------+
    
    | 12h-  | ERRSEG     | Segment to error            | See note  |
    
    | 13h   |            | interrupt vector.           | below.    |
    
    +-------+-----------+-----------------------------+-----------+
    
    | 14h-  | EXTOFF     | Offset to external          |           |
    
    | 15h   |            | interrupt vector.           |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 16h-  | EXTSEG     | Segment to external         |           |
    
    | 17h   |            | interrupt vector.           |           |
    
    +-------+------------+-----------------------------+-----------+
    
    | 18h-  | SCCBAS     | SCC base register address;  |           |
    
    | 19h   |            | set by the Realtime         |           |
    
    |       |            | Control Microcode.          |           |
    
    +-------+------------+-----------------------------+-----------+
    
    

    Note:

    The error interrupt is equivalent to the Zilog SCC special receive condition interrupt.

    RS-422-A Port Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      0Bh        Resource block descriptor
    
      RS4TSK     Owner task number
    
      RS4NUM     RS-422-A port number
    
      xxxOFF     Requested Interrupt vector offset (dependent
    
                 on type of service)
    
      xxxSEG     Requested interrupt vector segment
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      SCCBAS     SCC base address
    
    

    Allocation of RS-422-A Ports

    Ownership of RS-422-A Ports

    Deallocation of RS-422-A Ports

    SVC 47h module is used to return ownership of the particular RS-422-A port to the control of the Realtime Control Microcode.

    Associated Interface Modules

    
    -------------------------------------------------
    
     Type            Invocation      Name
    
    -------------------------------------------------
    
     PROM Service    INT A2h         SCCRESET
    
    
    
     PROM Service    INT A4h         SCCREGS
    
    
    
     Diagnostic      AH = 09h,       CONFIGURE
    
     Test            INT = FEh       SCC CHANNEL
    
    
    
     Service         AH = 00h,       Half Rate
    
     Interrupt       INT = 74h       Select Control
    
    
    
     Service         AH = 01h,       Transmit Control
    
     Interrupt       INT = 74h
    
    
    
     Service         AH = 02h,       RTS/DTR Control
    
     Interrupt       INT = 74h
    
    
    
     Service         AH = 03h,       Query External/Status
    
     Interrupt       INT = 74h       Inputs
    
    
    
     Service         AH = 04h,       External/Status
    
     Interrupt       INT = 74h       Interrupt Control
    
    
    
     Service         AH = 05h,       Clear External/Status
    
     Interrupt       INT = 74h       Interrupt
    
    
    
     Service         AH = 06h,       Clocking Option
    
     Interrupt       INT = 74h       Control (Realtime
    
                                     Control Microcode 1.5
    
                                     only)
    
    

    Resource Conflicts Table

    The conflicts between resources is defined in the following table, assuming no custom interface boards are used:

    
    ------------------------------------------------------------------------
    
    The allocation of:    Prohibits the allocation of:
    
    ------------------------------------------------------------------------
    
    SCC/CIO package 0     SCC port 0, CIO port 0, RS-232-C port 0,
    
                          RS-422-A port 0
    
    
    
    SCC/CIO package 1     SCC port 1, CIO port 1, RS-232-C port 1,
    
                          RS-422-A port 1
    
    
    
    RS-232-C port 0       SCC port 0, CIO port 0, SCC/CIO package 0,
    
                          RS-422-A port 0
    
    
    
    RS-232-C port 1       SCC port 1, CIO port 1, SCC/CIO package 1,
    
                          RS-422-A port 1
    
    
    
    RS-232-C port 2       SCC port 2, CIO port 2, CIO port 3
    
    
    
    RS-232-C port 3       SCC port 3, CIO port 2, CIO port 3
    
    
    
    RS-232-C port 4       SCC port 4, CIO port 2, CIO port 3,
    
                          RS-422-A port 4
    
    
    
    RS-232-C port 5       SCC port 5, CIO port 2, CIO port 3,
    
                          RS-422-A port 5
    
    
    
    RS-232-C port 6       SCC port 6, CIO port 2, CIO port 3,
    
                          RS-422-A port 6
    
    
    
    RS-232-C port 7       SCC port 7, CIO port 2, CIO port 3,
    
                          RS-422-A port 7
    
    
    
    ------------------------------------------------------------------------
    
    The allocation of:    Prohibits the allocation of:
    
    ------------------------------------------------------------------------
    
    RS-422-A port 0       SCC port 0, CIO port 0, SCC/CIO package 0,
    
                          RS-232-C port 0
    
    
    
    RS-422-A port 1       SCC port 1, CIO port 1, SCC/CIO package 1,
    
                          RS-232-C port 1
    
    
    
    RS-422-A port 4       SCC port 4, CIO port 3, RS-232-C port 4
    
    
    
    RS-422-A port 5       SCC port 5, CIO port 3, RS-232-C port 5
    
    
    
    RS-422-A port 6       SCC port 6, CIO port 3, RS-232-C port 6
    
    
    
    RS-422-A port 7       SCC port 7, CIO port 3, RS-232-C port 7
    
    
    
    SCC port 0            SCC/CIO package 0, RS-232-C port 0, RS-422-A
    
                          port 0
    
    
    
    SCC port 1            SCC/CIO package 1, RS-232-C port 1, RS-422-A
    
                          port 1
    
    
    
    SCC port 2            RS-232-C port 2
    
    
    
    SCC port 3            RS-232-C port 3
    
    
    
    SCC port 4            RS-232-C port 4, RS-422-A port 4
    
    
    
    SCC port 5            RS-232-C port 5, RS-422-A port 5
    
    
    
    SCC port 6            RS-232-C port 6, RS-422-A port 6
    
    
    
    SCC port 7            RS-232-C port 7, RS-422-A port 7
    
    
    
    CIO port 0            SCC/CIO package 0, RS-232-C port 0,
    
                          RS-422-A port 0
    
    
    
    CIO port 1            SCC/CIO package 1, RS-232-C port 1,
    
                          RS-422-A port 1
    
    
    
    CIO port 2            RS-232-C port 2, RS-232-C port 3, RS-232-C port 4,
    
                          RS-232-C port 5, RS-232-C port 6, RS-232-C port 7
    
    
    
    CIO port 3            RS-232-C port 2, RS-232-C port 3, RS-232-C port 4,
    
                          RS-232-C port 5, RS-232-C port 6, RS-232-C port 7
    
                          RS-422-A port 4, RS-422-A port 5, RS-422-A port 6,
    
                          RS-422-A port 7
    
    

    System Unit Communications

    Any co-processor adapter application task may interrupt the system unit. The co-processor adapter operates in the shared interrupt mode so multiple co-processor adapters may be assigned to the same interrupt level.

    Two services are provided so tasks can interrupt the system unit: the INTPC SVC and the INTPCL PROM service.

    The INTPC SVC provides the user with a higher-level routine to interrupt the system unit. INTPC provides options to retry, request a restart of the system unit, "WAIT" the requesting task at the completion of the interrupt, and reset the "BUSY" and "OUTPUT BUFFER BUSY" primary status bits.

    The INTPCL PROM Service provides the task with a low-level routine to interrupt the system unit with no retry logic imbedded within the routine.

    The task should use the available interface routines to interrupt the system unit.

    To interrupt the system unit without using the provided services, the application task must execute the following:

    1. Check until the interrupt ID byte (INTID) in the interface block contains FFh. A value of FFh indicates the system unit is waiting to process the next interrupt.

    2. If FFh is the value found, proceed to Step 3. If a value other than FFh is found, continue checking until FFh value is found.

    3. Write the requesting task's task number in the interrupt ID byte (INTID) in the interface block.

    4. Write the requesting task's task number in the I/O port 12h Task Register. This causes an interrupt to the system unit.

    5. The system unit's acceptance of the interrupt is indicated by the system unit writing FFh to the INTID in the interface block.

    Associated Interface Modules

    
    --------------------------------------------
    
     Type            Invocation      Name
    
    --------------------------------------------
    
     PROM Service    INT A0h         INTPCL
    
    
    
     SVC             INT 56h,        INTPC
    
                     AH=37h
    
    

    Additional Task Services

    Certain services are provided via IBM-supported software that perform miscellaneous functions frequently required by an application task. These services are provided to make task writing easier.

    Associated Interface Modules

    
    ------------------------------------------------------
    
     Type            Invocation      Name
    
    ------------------------------------------------------
    
     PROM Service    INT B6h         SEG2PAGL
    
    
    
     PROM Service    INT B8h         PAG2SEGL
    
    
    
     PROM Service    INT C0h         Pointer to EBCDIC-
    
                                     ASCII table
    
    
    
     PROM Service    INT C2h         EBC2ASC
    
    
    
     PROM Service    INT C4h         ASC2EBC
    
    
    
     PROM Service    INT C6h         ADDINTRA
    
    
    
     PROM Service    INT C8h         REMINTRA
    
    
    
     PROM Service    INT CAh         ADDINTER
    
    
    
     PROM Service    INT CCh         REMINTER
    
    
    
     SVC             INT 56h,        READVEC
    
                     AH = 42h
    
    
    
     SVC             INT 56h,        QFREEST
    
                     AH = 49h
    
    
    
     Service         INT 60h         SEG2PAG
    
     Interrupt
    
    
    
     Service         INT 62h         PAG2SEG
    
     Interrupt
    
    
    
     Service         INT 70h         TRANSEG
    
     Interrupt
    
    

    First-Level Interrupt Handling

    The Realtime Control Microcode receives all interrupts, both hardware and software, and is responsible for processing them.

    Interrupt Handling

    The Realtime Control Microcode initializes interrupt vectors for each I/O interrupt to point to the Realtime Control Microcode first-level interrupt handler. When an application task requests a resource, the resource block contains the addresses of the task routines to handle interrupts for that particular resource. The Realtime Control Microcode has taken the task's interrupt handler addresses from the resource block and stored them in a separate internal table. When an I/O interrupt occurs, the Realtime Control Microcode gets control and performs a FAR CALL to the task's interrupt handler using the Realtime Control Microcode's first-level interrupt handler.

    Hardware Interrupt Processing

    Consider the following characteristics of Realtime Control Microcode first-level hardware interrupt processing when writing your application task I/O interrupt handlers:

    Software Timer Interrupt Handling

    When a timer times out, a FAR CALL is made to the vector supplied by the user. The routine at that vector must execute a FAR RETURN when the routine finishes.

    Command Interrupt Handling

    When the Realtime Control Microcode receives a task interrupt from the system unit, it sets the task busy and the output buffer busy in "primary status," then executes a CALL FAR to the subroutine pointed to by CVECT in the task header. The subroutine should POST the task with the new Command Post, and turn off the "output buffer busy" and the "busy bit" in the "primary status byte" for the task. The subroutine must also turn off the task's "error bit" in "primary status." When the subroutine is finished, it must execute a RET FAR instruction to return to the Realtime Control Microcode.

    Software Interrupt Handling

    Consider the following characteristics of Realtime Control Microcode first-level interrupt processing when handling software interrupts:

    Associated Interface Modules

    None


    Asynchronous Error Handling

    Asynchronous errors are those errors or exceptional conditions that occur unexpectedly. Because they may occur at any given time, the Realtime Control Microcode must continuously monitor for their occurrence. In contrast, an SVC error is not asynchronous because it may occur only when the call is processed. Therefore, the possibility of its occurrence can be anticipated, and appropriate error handling is done at the time the call finishes executing.

    Asynchronous error and exception conditions are detected by the Realtime Control Microcode. The handling of the error is performed by the Realtime Control Microcode unless a task makes special arrangements before the error occurrence to handle the error if it occurs. Occurrence of an asynchronous error causes the Realtime Control Microcode to jump to the appropriate error handler interrupt vector (odd vectors from 0EFh - FFh) in the following list.

    This section describes how asynchronous error and exception conditions are handled by the Realtime Control Microcode and application tasks that execute on the co-processor adapter.

    List of Asynchronous Error Conditions

    Following are the types of error conditions that are detected:

    
      Divide by Zero Interrupt                 Interrupt EFh
    
    
    
      Bounds Error Interrupt                   Interrupt F1h
    
    
    
      INTO Interrupt                           Interrupt F3h
    
    
    
      Operation code check (also               Interrupt F5h
    
      escape (ESC) operation code check)
    
    
    
      Watchdog timer expiration                Interrupt F7h
    
    
    
      Co-processor adapter storage parity      Interrupt F9h
    
      check error
    
    

    Following are the types of exception conditions that are detected:

    
      Non-maskable interrupt from system unit  Interrupt FBh
    
    
    
      Compare degate detect (system unit       Interrupt FDh
    
      initial program load detect)
    
    
    
      System unit channel check or lost        Interrupt FFh
    
      refresh detect
    
    

    Realtime Control Microcode Asynchronous Error Handling

    When one of the preceding asynchronous conditions is detected by the Realtime Control Microcode, the condition is handled in the following manner:

    The Realtime Control Microcode executes an INT EFh - FEh (depending on the error), and each task that acquired the associated interrupt vector is given control by the Realtime Control Microcode. Each task has the option of handling the error itself in whole or in part or letting the Realtime Control Microcode handle the error. If the Realtime Control Microcode processes the error, it checks to determine if an interrupt handler was executing. If not, the current task in execution is stopped, and the Realtime Control Microcode performs the following:

    If an interrupt handler was executing, the Realtime Control Microcode cannot determine which task was executing; therefore, all tasks are stopped regardless of their permanent status. Each error condition is handled as follows:

    Divide by Zero Interrupt

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector EFh. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    Bounds Error Interrupt

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector F1h. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    INTO Interrupt

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector F3h. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    Operation Code Check Error

    If an operation code check error occurs, the Realtime Control Microcode gives control to any task that has acquired interrupt vector F5h. When control is returned to the Realtime Control Microcode, if AL = 00, no further action is taken. Otherwise, the Realtime Control Microcode's "error" bit in the primary status byte in the interface block is set. The secondary status of the Realtime Control Microcode includes the address of the byte after the byte with the bad opcode. This should be sufficient for most programmers to start their debug. The system unit is interrupted with the error notification.

    Watchdog Timer Expiration

    For watchdog timer errors, the Realtime Control Microcode gives control to any task that has acquired interrupt vector F7h. When control is returned to the Realtime Control Microcode, if AL = 00, no further action is taken. Otherwise, all tasks are stopped. The system unit is interrupted by hardware.

    Co-Processor Adapter Storage Parity Check Error

    This error is handled the same as the operation code check error processing except that owners of interrupt vector F9h are given control.

    Non-Maskable Interrupt from the System Unit

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector FBh. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    Compare Degate Detect

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector FDh. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    System Unit Channel Check or Lost Refresh Detect

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector FFh. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    Application Task Error Handling

    If a task needs to handle any of these errors, the mechanism for doing so is to acquire the specific user interrupt vector for that error. If the error occurs, the Realtime Control Microcode passes control through that interrupt vector before it processes the interrupt. Your application task can expect interrupts to be enabled and all non-maskable interrupts (NMIs) to be masked off when it receives control. The Realtime Control Microcode handles the unmasking of NMIs when control is passed back from your task. If your task does not need the Realtime Control Microcode to do any further error handling, it should set the AL register to 0. It is permissible for the task to do some processing and still request that the Realtime Control Microcode complete the processing of the error.

    Associated Interface Modules

    None.


    Chapter 11. Interrupt Vector Table Map for the Realtime Interface Co-Processor, Multiport, and Multiport/2 Adapters

    This chapter provides information about the Interrupt Vector Table Map for the Realtime Interface Co-Processor, the Realtime Interface Co-Processor Multiport, and the Realtime Interface Co-Processor Multiport/2. (For related information for the Realtime Interface Co-Processor Portmaster Adapter/A or the Realtime Interface Co-Processor Multiport Adapter, Model 2, see Chapter 13. "Interrupt Vector Table Map for the Portmaster Adapter/A and Multiport Adapter, Model 2".)

    The Interrupt Vector Table Map provides the link between an interrupt vector number code and the procedure assigned to service interrupts associated with that vector number code. The Interrupt Vector Table occupies the first 1024 bytes of co-processor adapter low memory beginning at location 00000h.

    Each table entry is a doubleword pointer that contains the address of the procedure assigned to service the associated interrupt number. The vector pointer is stored in offset: segment format. Because each entry is four bytes long, the location of the actual vector can be calculated by multiplying the interrupt vector number code by four.

    Some interrupts have a hardware device as a source. If that hardware device is not present on a specific co-processor adapter, the associated interrupt vector is reserved.

    
    ----------------------------------------------------------------
    
     Vector Number     Function
    
     Code
    
    ----------------------------------------------------------------
    
    
    
         00h           Divide Error
    
         01h           Single Step Interrupt
    
         02h           Non-maskable Interrupt (NMI)
    
         03h           Breakpoint
    
         04h           INTO Detected Overflow
    
    
    
         05h           Array Bounds Exception
    
         06h           Undefined Operation Code
    
         07h           Escape (ESC) Operation Code Exception
    
         08h           80186 Timer 0 (Software Timer Control)
    
         09h           Reserved
    
    
    
         0Ah           DMA 0
    
         0Bh           DMA 1
    
         0Ch           INT 0 (Shared Storage Interface Chip)
    
         0Dh           Reserved
    
         0Eh           INT 2
    
    
    
         0Fh           Reserved
    
         10h           Reserved
    
         11h           Reserved
    
         12h           80186 Timer 1 (time slice control)
    
         13h           80186 Timer 2 (80186 Timer 0 and 1
    
                       Prescaler)
    
    
    
         14h           Reserved
    
         15h           Reserved
    
         16h           Reserved
    
         17h           Reserved
    
         18h           Reserved
    
    
    
         19h           Reserved
    
         1Ah           Reserved
    
         1Bh           Reserved
    
         1Ch           Reserved
    
         1Dh           Reserved
    
    
    
         1Eh           Reserved
    
         1Fh           Reserved
    
         20h           SCC Port 1 Transmit Buffer Empty
    
         21h           User-requestable Interrupt
    
         22h           SCC Port 1 External Status
    
    
    
         23h           User-requestable Interrupt
    
         24h           SCC Port 1 Receiver Ready
    
         25h           User-requestable Interrupt
    
         26h           SCC Port 1 Special Receive Condition
    
         27h           User-requestable Interrupt
    
    
    
    ----------------------------------------------------------------
    
     Vector Number     Function
    
     Code
    
    ----------------------------------------------------------------
    
         28h           SCC Port 0 Transmit Buffer Empty
    
         29h           User-requestable Interrupt
    
         2Ah           SCC Port 0 External Status
    
         2Bh           User-requestable Interrupt
    
         2Ch           SCC Port 0 Receiver Ready
    
    
    
         2Dh           User-requestable Interrupt
    
         2Eh           SCC Port 0 Special Receive Condition
    
         2Fh           User-requestable Interrupt
    
         30h           CIO Port 0 Bit 0
    
         31h           User-requestable Interrupt
    
    
    
         32h           CIO Port 0 Bit 1
    
         33h           User-requestable Interrupt
    
         34h           CIO Port 0 Bit 2
    
         35h           User-requestable Interrupt
    
         36h           CIO Port 0 Bit 3
    
    
    
         37h           User-requestable Interrupt
    
         38h           CIO Port 0 Bit 4
    
         39h           User-requestable Interrupt
    
         3Ah           CIO Port 0 Bit 5
    
         3Bh           User-requestable Interrupt
    
    
    
         3Ch           CIO Port 0 Bit 6
    
         3Dh           User-requestable Interrupt
    
         3Eh           Reserved
    
         3Fh           User-requestable Interrupt
    
         40h           CIO Port 1 Bit 0
    
    
    
         41h           User-requestable Interrupt
    
         42h           CIO Port 1 Bit 1
    
         43h           User-requestable Interrupt
    
         44h           CIO Port 1 Bit 2
    
         45h           User-requestable Interrupt
    
    
    
         46h           CIO Port 1 Bit 3
    
         47h           User-requestable Interrupt
    
         48h           CIO Port 1 Bit 4
    
         49h           User-requestable Interrupt
    
         4Ah           CIO Port 1 Bit 5
    
    
    
         4Bh           User-requestable Interrupt
    
         4Ch           CIO Port 1 Bit 6
    
         4Dh           User-requestable Interrupt
    
         4Eh           Reserved
    
         4Fh           User-requestable Interrupt
    
    
    
    ----------------------------------------------------------------
    
     Vector Number     Function
    
     Code
    
    ----------------------------------------------------------------
    
         50h           CIO Port 0 Timer 3 (Watchdog Timer)
    
         51h           User-requestable Interrupt
    
         52h           CIO Port 0 Timer 2 (User-requestable
    
                       as Hardware Timer 1)
    
         53h           User-requestable Interrupt
    
         54h           CIO port 0 Timer 1 (User-requestable
    
                       as Hardware Timer 0)
    
    
    
         55h           User-requestable Interrupt
    
         56h           Supervisor Call Interrupt
    
         57h           User-requestable Interrupt
    
         58h           Reserved
    
         59h           User-requestable Interrupt
    
    
    
         5Ah           Reserved
    
         5Bh           User-requestable Interrupt
    
         5Ch           Reserved
    
         5Dh           User-requestable Interrupt
    
         5Eh           Reserved
    
    
    
         5Fh           User-requestable Interrupt
    
         60h           SEG2PAG Service Interrupt
    
         61h           User-requestable Interrupt
    
         62h           PAG2SEG Service Interrupt
    
         63h           User-requestable Interrupt
    
    
    
         64h           POSTI Service Interrupt
    
         65h           User-requestable Interrupt
    
         66h           RESUMEI Service Interrupt
    
         67h           User-requestable Interrupt
    
         68h           CANCELI Service Interrupt
    
    
    
         69h           User-requestable Interrupt
    
         6Ah           RECQUEUE Service Interrupt
    
         6Bh           User-requestable Interrupt
    
         6Ch           ADDQUEUE Service Interrupt
    
         6Dh           User-requestable Interrupt
    
    
    
         6Eh           REMQUEUE Service Interrupt
    
         6Fh           User-requestable Interrupt
    
         70h           TRANSEG Service Interrupt
    
         71h           User-requestable Interrupt
    
         72h           ESIR Service Interrupt
    
    
    
         73h           User-requestable Interrupt
    
         74h           LCLS Service Interrupt
    
         75h           User-requestable Interrupt
    
         76h           Reserved
    
         77h           User-requestable Interrupt
    
    
    
    ----------------------------------------------------------------
    
     Vector Number     Function
    
     Code
    
    ----------------------------------------------------------------
    
         78h           Reserved
    
         79h           User-requestable Interrupt
    
         7Ah           Reserved
    
         7Bh           User-requestable Interrupt
    
         7Ch           Reserved
    
    
    
         7Dh           User-requestable Interrupt
    
         7Eh           Reserved
    
         7Fh           User-requestable Interrupt
    
         80h           SCC 3 Transmit Buffer Empty (if present)
    
         81h           User-requestable Interrupt
    
    
    
         82h           SCC 3 External Status (if present)
    
         83h           User-requestable Interrupt
    
         84h           SCC 3 Receiver Ready (if present)
    
         85h           User-requestable Interrupt
    
         86h           SCC 3 Special Receive Condition
    
                       (if present)
    
    
    
         87h           User-requestable Interrupt
    
         88h           SCC 2 Transmit Buffer Empty (if present)
    
         89h           User-requestable Interrupt
    
         8Ah           SCC 2 External Status (if present)
    
         8Bh           User-requestable Interrupt
    
    
    
         8Ch           SCC 2 Receiver Ready (if present)
    
         8Dh           User-requestable Interrupt
    
         8Eh           SCC 2 Special Receive Condition
    
                       (if present)
    
         8Fh           User-requestable Interrupt
    
         90h           SCC 5 Transmit Buffer Empty (if present)
    
    
    
         91h           User-requestable Interrupt
    
         92h           SCC 5 External Status (if present)
    
         93h           User-requestable Interrupt
    
         94h           SCC 5 Receiver Ready (if present)
    
         95h           User-requestable Interrupt
    
    
    
         96h           SCC 5 Special Receive Condition
    
                       (if present)
    
         97h           User-requestable Interrupt
    
         98h           SCC 4 Transmit Buffer Empty (if present)
    
         99h           User-requestable Interrupt
    
         9Ah           SCC 4 External Status (if present)
    
    
    
         9Bh           User-requestable Interrupt
    
         9Ch           SCC 4 Receiver Ready (if present)
    
         9Dh           User-requestable Interrupt
    
         9Eh           SCC 4 Receive Condition (if present)
    
         9Fh           User-requestable Interrupt
    
    
    
    ----------------------------------------------------------------
    
     Vector Number     Function
    
     Code
    
    ----------------------------------------------------------------
    
         A0h           INTPCL PROM Service
    
         A1h           User-requestable Interrupt
    
         A2h           SCCRESET PROM Service
    
         A3h           User-requestable Interrupt
    
         A4h           SCCREGS PROM Service
    
    
    
         A5h           User-requestable Interrupt
    
         A6h           CIOREGS PROM Service
    
         A7h           User-requestable Interrupt
    
         A8h           CIOTMR PROM Service
    
         A9h           User-requestable Interrupt
    
    
    
         AAh           DMACONNECT PROM Service
    
         ABh           User-requestable Interrupt
    
         ACh           DMASUPPORT PROM Service
    
         ADh           User-requestable Interrupt
    
         AEh           DMAREGS PROM Service
    
    
    
         AFh           User-requestable Interrupt
    
         B0h           DMASTOP PROM Service
    
         B1h           User-requestable Interrupt
    
         B2h           DMAADDR PROM Service
    
         B3h           User-requestable Interrupt
    
    
    
         B4h           Reserved
    
         B5h           User-requestable Interrupt
    
         B6h           SEG2PAGL PROM Service
    
         B7h           User-requestable Interrupt
    
         B8h           PAG2SEGL PROM Service
    
    
    
         B9h           User-requestable Interrupt
    
         BAh           Reserved
    
         BBh           User-requestable Interrupt
    
         BCh           Reserved
    
         BDh           User-requestable Interrupt
    
    
    
         BEh           Reserved
    
         BFh           User-requestable Interrupt
    
         C0h           Reserved (Pointer to EBCDIC-to-ASCII
    
                       Table)
    
         C1h           User-requestable Interrupt
    
         C2h           EBC2ASC PROM Service
    
    
    
         C3h           User-requestable Interrupt
    
         C4h           ASC2EBC PROM Service
    
         C5h           User-requestable Interrupt
    
         C6h           ADDINTRA PROM Service
    
         C7h           User-requestable Interrupt
    
    
    
    ----------------------------------------------------------------
    
     Vector Number     Function
    
     Code
    
    ----------------------------------------------------------------
    
    
    
         C8h           REMINTRA PROM Service
    
         C9h           User-requestable Interrupt
    
         CAh           ADDINTER PROM Service
    
         CBh           User-requestable Interrupt
    
         CCh           REMINTER PROM Service
    
    
    
         CDh           User-requestable Interrupt
    
         CEh           Reserved
    
         CFh           User-requestable Interrupt
    
         D0h           Reserved
    
         D1h           User-requestable Interrupt
    
    
    
         D2h           Reserved
    
         D3h           User-requestable Interrupt
    
         D4h           Reserved
    
         D5h           User-requestable Interrupt
    
         D6h           Reserved
    
    
    
         D7h           User-requestable Interrupt
    
         D8h           Reserved
    
         D9h           User-requestable Interrupt
    
         DAh           Reserved
    
         DBh           User-requestable Interrupt
    
    
    
         DCh           Reserved
    
         DDh           User-requestable Interrupt
    
         DEh           Reserved
    
         DFh           User-requestable Interrupt
    
         E0h           SCC Port 7 Transmit Buffer Empty
    
                       (if present)
    
    
    
         E1h           User-requestable Interrupt
    
         E2h           SCC Port 7 External Status (if present)
    
         E3h           User-requestable Interrupt
    
         E4h           SCC Port 7 Receiver Ready (if present)
    
         E5h           User-requestable Interrupt
    
    
    
         E6h           SCC Port 7 Special Receive Condition
    
                       (if present)
    
         E7h           User-requestable Interrupt
    
         E8h           SCC Port 6 Transmit Buffer Empty
    
                       (if present)
    
         E9h           User-requestable Interrupt
    
         EAh           SCC Port 6 External Status (if present)
    
    
    
    ----------------------------------------------------------------
    
     Vector Number     Function
    
     Code
    
    ----------------------------------------------------------------
    
    
    
         EBh           User-requestable Interrupt
    
         ECh           SCC Port 6 Receiver Ready (if present)
    
         EDh           User-requestable Interrupt
    
         EEh           SCC Port 6 Special Receive Condition
    
                       (if present)
    
         EFh           Divide Error Exception Vector
    
                       User-requestable Interrupt
    
         F0h           CIO 1 Timer 3 (User-Requestable as
    
                       Hardware Timer 4, if present)
    
         F1h           Array Bounds Exception Vector
    
                       User-requestable Interrupt
    
         F2h           CIO 1 Timer 2 (User-Requestable as
    
                       Hardware Timer 3, if present)
    
         F3h           Interrupt on Overflow Exception Vector
    
                       User-requestable Interrupt
    
         F4h           CIO 1 Timer 1 (User-requestable as
    
                       Hardware Timer 2, if present)
    
    
    
         F5h           Non-valid Opcode Error Detected Vector
    
                       User-requestable Interrupt
    
         F6h           CIO 1 Timer Error Vector (if present)
    
         F7h           Watchdog Error Detected
    
                       Vector User-requestable Interrupt
    
         F8h           CIO Port 2 (if present)
    
         F9h           Parity Error Detected Vector
    
                       User-requestable Interrupt
    
    
    
         FAh           CIO Port 3 (if present)
    
         FBh           NMI from System Unit Vector
    
                       User-requestable Interrupt
    
         FCh           Reserved
    
         FDh           Compare Degate Detected Vector
    
                       User-requestable Interrupt
    
         FEh           Diagnostic Test Subroutine Call
    
         FFh           System Unit Channel Check
    
                       or System Unit Lost
    
                       Refresh Detected Vector
    
                       User-requestable Interrupt
    
    

    Chapter 12. Software Functions for the Portmaster Adapter/A and Multiport Adapter, Model 2

    This chapter describes the following for the Realtime Interface Co-Processor Portmaster Adapter/A and the Realtime Interface Co-Processor Multiport Adapter, Model 2:

    Associated data structures and a list of associated interface modules are also included.

    For related information for the Realtime Interface Co-Processor, the Realtime Interface Co-Processor Multiport, or the Realtime Interface Co-Processor Multiport/2, see Chapter 10. "Software Functions for the Realtime Interface Co-Processor, Multiport, and Multiport/2 Adapters".


    Task Management

    The Realtime Control Microcode is the multitasking supervisor that is loaded to the co-processor adapter as Task 0. The Realtime Control Microcode controls the execution of all application tasks on the co-processor adapter. There may be up to 248 concurrent tasks executing on any of 255 priorities.

    Management Tools

    Management tools used by the Realtime Control Microcode to supervise tasks:

    Data Structures

    The Realtime Control Microcode and application tasks use data structures (control blocks) to communicate and control the actions and states of the application tasks. The task writer should be familiar with the following data structures:

    PROM Work Area

    Purpose:
    Used for scratch memory during the execution of the adapter's PROM power-on tests, and initializes the return pointer (RETPTR), for task 0 to return to PROM, and the extended PROM work area pointer (XWRKPTR), which points to the extended PROM work area.

    Location:
    Page 0 starting at location 0400h

    Size:
    2Eh bytes

    Initialization:
    The PROM power-on test microcode sets the following values during power-on/reset initialization:

    The format of the PROM work area is as follows.

    
    
    
    +-------------------------------------------------------------------+
    
    
    
    | PROM Work Area                                                    |
    
    
    
    +-------+------------+----------------------------+-----------------+
    
    
    
    | Byte  | Field Name | Description                | Comments        |
    
    
    
    +-------+------------+----------------------------+-----------------+
    
    | 0400h-| RETPTR     | 80186 logical address      | Bytes 2-3 = PROM|
    
    | 0403h |            | pointer for task 0 to      | Segment         |
    
    |       |            | return to PROM.            |                 |
    
    +-------+------------+----------------------------+-----------------+
    
    | 0404h-| Reserved   | Reserved                   | For PROM use    |
    
    | 040Dh |            |                            | only.           |
    
    +-------+------------+----------------------------+-----------------+
    
    | 040Eh-| XWRKPTR    | 80186 logical address      |                 |
    
    | 0411h |            | pointer to extended PROM   |                 |
    
    |       |            | work area.                 |                 |
    
    +-------+------------+----------------------------+-----------------+
    
    | 0412h-| Reserved   | Reserved                   | For PROM use    |
    
    | 042Dh |            |                            | only.           |
    
    +-------+------------+----------------------------+-----------------+
    
    

    Extended PROM Work Area

    The extended PROM work area provides additional storage for use by the adapter's PROM power-on tests.

    Purpose:
    Used for scratch memory during the execution of the adapter's PROM power-on tests and to pass information back to the system unit.

    Location:
    Varies depending on the size of memory installed on the adapter. The extended PROM work area is pointed to by the XWRKPTR field of the PROM work area.

    Size:
    20h bytes

    Initialization:
    The PROM power-on test microcode sets the PCD_BASE value during power-on/reset initialization.

    The format of the extended PROM work area is as follows:

    
              +----------------------------------------------------+
    
    
    
              | Extended PROM Work Area                            |
    
    
    
              +------------+-------------------------+-------------+
    
    
    
     Offset   | Field Name | Description             | Comments    |
    
    
    
              +------------+-------------------------+-------------+
    
     00h-03h  | PCD_BASE   | 80186 logical address   |             |
    
              |            | pointer to the port     |             |
    
              |            | configuration           |             |
    
              |            | descriptor (PCD).       |             |
    
              +------------+-------------------------+-------------+
    
     04h-1Fh  | Reserved   | Reserved                | For PROM    |
    
              |            |                         | use only.   |
    
              +------------+-------------------------+-------------+
    
    

    Port Configuration Descriptor (PCD)

    The PCD is used to describe the hardware and electrical interfaces of the adapter and its attached interface board.

    Purpose:
    Describes the adapter and interface board hardware and electrical interfaces.

    Location:
    Pointed to by PCD_BASE entry of Extended PROM Work Area.

    Size:
    EAh bytes + 3Bh bytes per communications port

    Initialization:
    The Port Configuration Descriptor is initialized during power-on/reset, and may also be reinitialized by the Diagnostic Service call INT FEh, with AH = 13h.

    The format of the Port Configuration Descriptor is as follows:

    
    
    
             +-----------------------------------------------------------------+
    
    
    
             |Port Configuration Descriptor                                    |
    
    
    
             +---------------+-----------------------+-------------------------+
    
    
    
     Offset  |Field Name     |Description            | Comments                |
    
    
    
             +---------------+-----------------------+-------------------------+
    
     00h     |LCLS_CONFORM   |Indicator that the     | 00h = Yes               |
    
             |               |Interface Board PROM   | FFh = No                |
    
             |               |contains data in the   |                         |
    
             |               |format required for    |                         |
    
             |               |LCLS support.          |                         |
    
             +---------------+-----------------------+-------------------------+
    
     01h     |PORT_COUNT     |Number of communication|                         |
    
             |               |ports on base card and |                         |
    
             |               |on interface board.    |                         |
    
             +---------------+-----------------------+-------------------------+
    
     02h-11h |CIO_BASE_ADR   |Base addresses of CIOs.| Two bytes per CIO.      |
    
             |               |                       | FFFFh if CIO not        |
    
             |               |                       | present.                |
    
             +---------------+-----------------------+-------------------------+
    
     12h-31h |SCC_BASE_ADR   |Base addresses of SCCs.| Two bytes per SCC.      |
    
             |               |                       | FFFFh if SCC is not     |
    
             |               |                       | present.  SCC is used   |
    
             |               |                       | to refer to any type of |
    
             |               |                       | serial communications   |
    
             |               |                       | controller.             |
    
             +---------------+-----------------------+-------------------------+
    
     32h-41h |SCC_REL_CIO    |SCCRELINIT Register    | Two bytes per CIO.      |
    
             |               |Addresses for CIOs.    |                         |
    
             +---------------+-----------------------+-------------------------+
    
     42h-61h |SCC_REL_SCC    |SCCRELINIT Register    | Two bytes per SCC.      |
    
             |               |Addresses for SCCs.    |                         |
    
             +---------------+-----------------------+-------------------------+
    
     62h-69h |DMAPIC_BASE_ADR|Base addresses of Gate | Two bytes per Gate      |
    
             |               |Arrays.                | Array.                  |
    
             +---------------+-----------------------+-------------------------+
    
     6Ah-89h |TX_DMA         |TX DMA Channel Number. | One byte per port.      |
    
             |               |                       | = 0h-FFh                |
    
             |               |                       |   FEh = 1 DMA Channel   |
    
             |               |                       |         per port        |
    
             |               |                       |         (configurable)  |
    
             |               |                       |   FFh = No DMA for TX   |
    
             +---------------+-----------------------+-------------------------+
    
     8Ah-A9h |RX_DMA         |RX DMA Channel Number. | One byte per port.      |
    
             |               |                       | = 0h-FFh                |
    
             |               |                       |   FFh = No DMA for RX   |
    
             |               |                       |   If TX_DMA = FEh, then |
    
             |               |                       |   RX_DMA entry contains |
    
             |               |                       |   channel number of     |
    
             |               |                       |   configurable channel. |
    
             +---------------+-----------------------+-------------------------+
    
     AAh-C9h |SYNC           | Indicates that port   | One byte per port.      |
    
             |               | has sync capability.  | 00h = Sync capability   |
    
             |               |                       |       present           |
    
             |               |                       | FFh = No sync capability|
    
             |               |                       |       present           |
    
             +---------------+-----------------------+-------------------------+
    
     CAh-E9h |INTERFACE      | Describes port        | One byte per port.      |
    
             |               | interface.            | 00h = RS232C            |
    
             |               |                       | 01h = RS422A            |
    
             |               |                       | 02h = V.35              |
    
             |               |                       | 03h = X.21              |
    
             |               |                       | 04h-FDh = Reserved      |
    
             |               |                       | FEh = Interface unknown |
    
             |               |                       | FFh = Configurable by   |
    
             |               |                       |       cable             |
    
             +---------------+-----------------------+-------------------------+
    
     EAh-    |PORT_INFO      | Describes port        | 3Bh bytes per port.     |
    
             |               | control signals and   | See following table.    |
    
             |               | wrap information.     |                         |
    
             +---------------+-----------------------+-------------------------+
    
    
    
    

    The PORT INFO field of the Port Configuration Descriptor contains control signal and wrap information for each communication port of the adapter and its attached interface board. The format of the PORT INFO field is as follows:

    
    
    
              +-----------------------------------------------------------------+
    
    
    
              |Port Information Field of the Port Configuration Descriptor      |
    
    
    
              +-------------+-------------------------=-------------------------+
    
    
    
     Offset   |Field Name   | Description             |   Comments              |
    
    
    
              +-------------+-------------------------+-------------------------+
    
     00h-01h  |LCLS_SUPPORT | Indicates which LCLS    | Reserved                |
    
              |             | services are supported. |                         |
    
              +-------------+-------------------------+-------------------------+
    
     02h-03h  |HRS(OUT)     | Port address or CIO port|                         |
    
              |  PORT_ADDR  | number if port type =   |                         |
    
              |             | 00h or 01h.             |                         |
    
              +-------------+-------------------------+-------------------------+
    
     04h      |HRS(OUT)     | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     05h      |HRS(OUT)     | Describes device which  | 00h = Port A or Port B  |
    
              |  PORT_TYPE  | controls this signal.   |       of CIO            |
    
              |             |                         | 01h = Port C of CIO     |
    
              |             |                         | 02h = any 8 bit read/   |
    
              |             |                         |       write register    |
    
              |             |                         | FFh = HRS(OUT) not      |
    
              |             |                         |       supported         |
    
              +-------------+-------------------------+-------------------------+
    
     06h      |HRS(OUT)     | Describes logical level | 00h = output logic 0 to |
    
              |  ACTIVATION | used to control this    |       activate HRS(OUT) |
    
              |             | signal.                 |       output logic 1 to |
    
              |             |                         |       deactivate        |
    
              |             |                         | 01h = output logic 1 to |
    
              |             |                         |       activate HRS(OUT) |
    
              |             |                         |       output logic 0 to |
    
              |             |                         |       deactivate        |
    
              +-------------+-------------------------+-------------------------+
    
     07h-08h  |TXBLK        | Port address or CIO port|                         |
    
              |  PORT_ADDR  | number if port type =   |                         |
    
              |             | 00h or 01h.             |                         |
    
              +-------------+-------------------------+-------------------------+
    
     09h      |TXBLK        | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     0Ah      |TXBLK        | Describes device which  | 00h = Port A or Port B  |
    
              |  PORT_TYPE  | controls this signal.   |       of CIO            |
    
              |             |                         | 01h = Port C of CIO     |
    
              |             |                         | 02h = any 8 bit read/   |
    
              |             |                         |       write register    |
    
              |             |                         | FEh = RTS is required to|
    
              |             |                         |       enable transmit   |
    
              |             |                         | FFh = TXBLK not         |
    
              |             |                         |       supported         |
    
              +-------------+-------------------------+-------------------------+
    
     0Bh      |TXBLK        | Describes logical level | 00h = output logic 0 to |
    
              |  ACTIVATION | used to control this    |       activate TXBLK    |
    
              |             | signal.                 |       output logic 1 to |
    
              |             |                         |       deactivate        |
    
              |             |                         | 01h = output logic 1 to |
    
              |             |                         |       activate TXBLK    |
    
              |             |                         |       output logic 0 to |
    
              |             |                         |       deactivate        |
    
              +-------------+-------------------------+-------------------------+
    
     0Ch-0Dh  |CLOCK        | Port address or CIO port|                         |
    
              |  PORT_ADDR  | number if port type =   |                         |
    
              |             | 00h or 01h.             |                         |
    
              +-------------+-------------------------+-------------------------+
    
     0Eh      |CLOCK        | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     0Fh      |CLOCK        | Describes device which  | 00h = Port A or Port B  |
    
              |  PORT_TYPE  | controls this signal.   |       of CIO            |
    
              |             |                         | 01h = Port C of CIO     |
    
              |             |                         | 02h = any 8 bit read/   |
    
              |             |                         |       write register    |
    
              |             |                         | FFh = CLOCK not         |
    
              |             |                         |       supported         |
    
              +-------------+-------------------------+-------------------------+
    
     10h      |CLOCK        | Describes logical level | 00h = output logic 0 to |
    
              |  ACTIVATION | used to control this    |       activate DTE CLK  |
    
              |             | signal.                 |       output logic 1 to |
    
              |             |                         |       activate DCE CLK  |
    
              |             |                         | 01h = output logic 1 to |
    
              |             |                         |       activate DTE CLK  |
    
              |             |                         |       output logic 0 to |
    
              |             |                         |       activate DCE CLK  |
    
              +-------------+-------------------------+-------------------------+
    
     11h-12h  |RTS          | Port address or CIO port| This field not used if  |
    
              |  PORT_ADDR  | number if port type =   | signal from SCC.        |
    
              |             | 00h or 01h.             |                         |
    
              +-------------+-------------------------+-------------------------+
    
     13h      |RTS          | Register bit position   | This field not used if  |
    
              |  BIT_NO     | for this signal.        | signal from SCC.        |
    
              +-------------+-------------------------+-------------------------+
    
     14h      |RTS          | Describes device which  | 00h = Port A or Port B  |
    
              |  PORT_TYPE  | controls this signal.   |       of CIO            |
    
              |             |                         | 01h = Port C of CIO     |
    
              |             |                         | 02h = any 8 bit read/   |
    
              |             |                         |       write register    |
    
              |             |                         | 03h = SCC               |
    
              |             |                         | FFh = RTS not supported |
    
              +-------------+-------------------------+-------------------------+
    
     15h      |RTS          | Describes logical level | 00h = output logic 0 to |
    
              |  ACTIVATION | used to control this    |       activate RTS      |
    
              |             | signal.                 |       output logic 1 to |
    
              |             |                         |       deactivate RTS    |
    
              |             |                         | 01h = output logic 1 to |
    
              |             |                         |       activate RTS      |
    
              |             |                         |       output logic 0 to |
    
              |             |                         |       deactivate RTS    |
    
              +-------------+-------------------------+-------------------------+
    
     16h-17h  |DTR          | Port address or CIO port| This field not used if  |
    
              |  PORT_ADDR  | number if port type =   | signal from SCC.        |
    
              |             | 00h or 01h.             |                         |
    
              +-------------+-------------------------+-------------------------+
    
     18h      |DTR          | Register bit position   | This field not used if  |
    
              |  BIT_NO     | for this signal.        | signal from SCC.        |
    
              +-------------+-------------------------+-------------------------+
    
     19h      |DTR          | Describes device which  | 00h = Port A or Port B  |
    
              |  PORT_TYPE  | controls this signal.   |       of CIO            |
    
              |             |                         | 01h = Port C of CIO     |
    
              |             |                         | 02h = any 8 bit read/   |
    
              |             |                         |       write register    |
    
              |             |                         | 03h = SCC               |
    
              |             |                         | FFh = DTR not supported |
    
              +-------------+-------------------------+-------------------------+
    
     1Ah      |DTR          | Describes logical level | 00h = output logic 0 to |
    
              |  ACTIVATION | used to control this    |       activate DTR      |
    
              |             | signal.                 |       output logic 1 to |
    
              |             |                         |       deactivate DTR    |
    
              |             |                         | 01h = output logic 1 to |
    
              |             |                         |       activate DTR      |
    
              |             |                         |       output logic 0 to |
    
              |             |                         |       deactivate DTR    |
    
              +-------------+-------------------------+-------------------------+
    
     1Bh-1Ch  |CONTROL      | Port address or CIO port|                         |
    
              |  PORT_ADDR  | number if port type =   |                         |
    
              |             | 00h or 01h.             |                         |
    
              +-------------+-------------------------+-------------------------+
    
     1Dh      |CONTROL      | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     1Eh      |CONTROL      | Describes device which  | 00h = Port A or Port B  |
    
              |  PORT_TYPE  | controls this signal.   |       of CIO            |
    
              |             |                         | 01h = Port C of CIO     |
    
              |             |                         | 02h = any 8 bit read/   |
    
              |             |                         |       write register    |
    
              |             |                         | FFh = CONTROL not       |
    
              |             |                         |       supported         |
    
              +-------------+-------------------------+-------------------------+
    
     1Fh      |CONTROL      | Describes logical level | 00h = output logic 0 to |
    
              |  ACTIVATION | used to control this    |       activate CONTROL  |
    
              |             | signal.                 |       output logic 1 to |
    
              |             |                         |       deactivate        |
    
              |             |                         | 01h = output logic 1 to |
    
              |             |                         |       activate CONTROL  |
    
              |             |                         |       output logic 0 to |
    
              |             |                         |       deactivate        |
    
              +-------------+-------------------------+-------------------------+
    
     20h      |RI           | CIO port number.        | 00h-22h = CIO port      |
    
              |  PORT_NO    |                         |           number        |
    
              |             |                         | FFh = RI not supported  |
    
              +-------------+-------------------------+-------------------------+
    
     21h      |RI           | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     22h      |RI           | Describes logical level | 00h = RI is active when |
    
              |  ACTIVATION | used to control this    |       read logic 0      |
    
              |             | signal.                 |       RI is not active  |
    
              |             |                         |       when read logic 1 |
    
              |             |                         | 01h = RI is active when |
    
              |             |                         |       read logic 1      |
    
              |             |                         |       RI is not active  |
    
              |             |                         |       when read logic 0 |
    
              +-------------+-------------------------+-------------------------+
    
     23h      |HRS(IN)      | CIO port number.        | 00h-22h = CIO port      |
    
              |  PORT_NO    |                         |           number        |
    
              |             |                         | FFh = HRS(IN) not       |
    
              |             |                         |       supported         |
    
              +-------------+-------------------------+-------------------------+
    
     24h      |HRS(IN)      | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     25h      |HRS(IN)      | Describes logical level | 00h = HRS(IN) is active |
    
              |  ACTIVATION | used to control this    |       when read logic 0 |
    
              |             | signal.                 |       HRS(IN) is not    |
    
              |             |                         |       active when read  |
    
              |             |                         |       read logic 1      |
    
              |             |                         | 01h = HRS(IN) is active |
    
              |             |                         |       when read logic 1 |
    
              |             |                         |       HRS(IN) is not    |
    
              |             |                         |       active when read  |
    
              |             |                         |       read logic 0      |
    
              +-------------+-------------------------+-------------------------+
    
     26h      |CTS          | Port Number for CTS.    | 00h-22h = CIO port      |
    
              |  PORT_NO    |                         |           number        |
    
              |             |                         | FEh = from SCC          |
    
              |             |                         | FFh = CTS not supported |
    
              +-------------+-------------------------+-------------------------+
    
     27h      |CTS          | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     28h      |CTS          | Describes logical level | 00h = CTS is active when|
    
              |  ACTIVATION | used to control this    |       read logic 0      |
    
              |             | signal.                 |       CTS is not active |
    
              |             |                         |       when read logic 1 |
    
              |             |                         | 01h = CTS is active when|
    
              |             |                         |       read logic 1      |
    
              |             |                         |       CTS is not active |
    
              |             |                         |       when read logic 0 |
    
              +-------------+-------------------------+-------------------------+
    
     29h      |DCD          | CIO port number.        | 00h-22h = CIO port      |
    
              |  PORT_NO    |                         |           number        |
    
              |             |                         | FEh = from SCC          |
    
              |             |                         | FFh = DCD not supported |
    
              +-------------+-------------------------+-------------------------+
    
     2Ah      |DCD          | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     2Bh      |DCD          | Describes logical level | 00h = DCD is active when|
    
              |  ACTIVATION | used to control this    |       read logic 0      |
    
              |             | signal.                 |       DCD is not active |
    
              |             |                         |       when read logic 1 |
    
              |             |                         | 01h = DCD is active when|
    
              |             |                         |       read logic 1      |
    
              |             |                         |       DCD is not active |
    
              |             |                         |       when read logic 0 |
    
              +-------------+-------------------------+-------------------------+
    
     2Ch      |DSR          | CIO port number.        | 00h-22h = CIO port      |
    
              |  PORT_NO    |                         |           number        |
    
              |             |                         | FEh = from SCC          |
    
              |             |                         | FFh = DSR not supported |
    
              +-------------+-------------------------+-------------------------+
    
     2Dh      |DSR          | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     2Eh      |DSR          | Describes logical level | 00h = DSR is active when|
    
              |  ACTIVATION | used to control this    |       read logic 0      |
    
              |             | signal.                 |       DSR is not active |
    
              |             |                         |       when read logic 1 |
    
              |             |                         | 01h = DSR is active when|
    
              |             |                         |       read logic 1      |
    
              |             |                         |       DSR is not active |
    
              |             |                         |       when read logic 0 |
    
              +-------------+-------------------------+-------------------------+
    
     2Fh      |INDICATE     | CIO port number.        | 00h-22h = CIO port      |
    
              |  PORT_NO    |                         |           number for    |
    
              |             |                         |           PROM and diags|
    
              |             |                         | FFh = DSR not supported |
    
              +-------------+-------------------------+-------------------------+
    
     30h      |INDICATE     | Register bit position   |                         |
    
              |  BIT_NO     | for this signal.        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     31h      |INDICATE     | Describes logical level | 00h = INDICATE is active|
    
              |  ACTIVATION | used to control this    |       when read logic 0 |
    
              |             | signal.                 |       INDICATE is not   |
    
              |             |                         |       active when read  |
    
              |             |                         |       logic 1           |
    
              |             |                         | 01h = INDICATE is active|
    
              |             |                         |       when read logic 1 |
    
              |             |                         |       INDICATE is not   |
    
              |             |                         |       active when read  |
    
              |             |                         |       logic 0           |
    
              +-------------+-------------------------+-------------------------+
    
     32h-3Ah  |WRAP PLUG    | Describes how the       | 00h = Signal not wrapped|
    
              |  INFORMATION| control signals are     | 01h = Signal wrapped to |
    
              |             | wrapped. For each signal|       TxD               |
    
              |             | listed below, use value | 02h = Signal wrapped to |
    
              |             | from table at right.    |       RTS               |
    
              |             |                         | 03h = Signal wrapped to |
    
              |             |                         |       DTR               |
    
              |             |                         | 04h = Signal wrapped to |
    
              |             |                         |       HRS(OUT)          |
    
              |             |                         | 05h = Signal wrapped to |
    
              |             |                         |       TXCOUT            |
    
              |             |                         | 06h = Signal wrapped to |
    
              |             |                         |       CONTROL           |
    
              +-------------+-------------------------+-------------------------+
    
     32h      |             | Wrap for RxD            |                         |
    
              +-------------+-------------------------+-------------------------+
    
     33h      |             | Wrap for CTS            |                         |
    
              +-------------+-------------------------+-------------------------+
    
     34h      |             | Wrap for DSR            |                         |
    
              +-------------+-------------------------+-------------------------+
    
     35h      |             | Wrap for DCD            |                         |
    
              +-------------+-------------------------+-------------------------+
    
     36h      |             | Wrap for HRS(IN)        |                         |
    
              +-------------+-------------------------+-------------------------+
    
     37h      |             | Wrap for TXCIN          |                         |
    
              +-------------+-------------------------+-------------------------+
    
     38h      |             | Wrap for RXCIN          |                         |
    
              +-------------+-------------------------+-------------------------+
    
     39h      |             | Wrap for RI             |                         |
    
              +-------------+-------------------------+-------------------------+
    
     3Ah      |             | Wrap for INDICATE       |                         |
    
              +-------------+-------------------------+-------------------------+
    
    

    Interface Block (IB)

    Purpose:
    Used as the central communication control block between the co-processor adapter and the system unit

    Location:
    Page 0 starting at location 0440h

    Size:
    MAXTASK + 3Dh bytes

    Initialization:
    Bootstrap Loader microcode sets the following values during power-on/reset initialization:
    The following values are initialized by the extended storage system unit support software:
    The Realtime Control Microcode sets the following values at Realtime Control Microcode initialization time:

    The format of the interface block is as follows:

    
    +---------------------------------------------------------------------+
    
    
    
    | Interface Block                                                     |
    
    
    
    +-------+-------------+---------------------+-------------------------+
    
    
    
    | Byte  | Field Name  | Description         |   Comments              |
    
    
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0440h | PC Select   | Indicates which     | = 0h-F8h                |
    
    |       | Byte        | task the system     |   Select task or        |
    
    |       |             | unit wants to       |   Realtime Control      |
    
    |       |             | interrupt.  This    |   Microcode             |
    
    |       |             | byte is written     |   when co-processor     |
    
    |       |             | by the system       |   adapter               |
    
    |       |             | unit prior to       |   interrupted by        |
    
    |       |             | interrupting the    |   host computer.        |
    
    |       |             | co-processor        | = FDh                   |
    
    |       |             | adapter.  After     |   Peer request pending  |
    
    |       |             | the Realtime        |   from host when        |
    
    |       |             | Control Microcode   |   co-processor adapter  |
    
    |       |             | or Bootstrap        |   interrupted by        |
    
    |       |             | Loader has          |   host computer.        |
    
    |       |             | received the        | = FEh                   |
    
    |       |             | interrupt, this     |   Error indicator set   |
    
    |       |             | byte is reset to    |   by Realtime Control   |
    
    |       |             | either FEh (to      |   Microcode after an    |
    
    |       |             | signal an error)    |   error is detected     |
    
    |       |             | or FFh (to acknow-  |   in a command.         |
    
    |       |             | ledge the           | = FFh                   |
    
    |       |             | interrupt).         |   Byte is empty and     |
    
    |       |             |                     |   used for interlock    |
    
    |       |             |                     |   purposes.             |
    
    |       |             |                     |   Initialized to        |
    
    |       |             |                     |   FFh by Bootstrap      |
    
    |       |             |                     |   Loader.               |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0441h | INTID       | Indicates which     | = 0h-F8h                |
    
    |       |             | task (or asynchro-  |   indicates which       |
    
    |       |             | nous error) is      |   task is               |
    
    |       |             | interrupting the    |   interrupting          |
    
    |       |             | system unit.        |   system unit.          |
    
    |       |             | This byte is        | = FDh                   |
    
    |       |             | written by the      |   Peer request pending  |
    
    |       |             | Realtime Control    |   from co-processor     |
    
    |       |             | Microcode or the    |   adapter when host is  |
    
    |       |             | Bootstrap Loader    |   interrupted.          |
    
    |       |             | prior to interrupt- | = FEh                   |
    
    |       |             | ing the host        |   Asynchronous          |
    
    |       |             | computer.  After    |   error interrupts.     |
    
    |       |             | the host computer   | = FFh                   |
    
    |       |             | receives the inter- |   Byte is empty and     |
    
    |       |             | rupt, this byte is  |   used for interlock    |
    
    |       |             | reset to FFh.       |   purposes.  Initial-   |
    
    |       |             |                     |   ized to FFh by        |
    
    |       |             |                     |   Bootstrap Loader.     |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0442h | SUPVID      | Realtime Control    |   Version of Realtime   |
    
    |       |             | Microcode identity  |   Control Microcode     |
    
    |       |             | byte.               |   resident in           |
    
    |       |             |                     |   co-processor adapter. |
    
    |       |             |                     |   00h = Realtime Control|
    
    |       |             |                     |   Microcode not loaded. |
    
    |       |             |                     |   01h = V1.0            |
    
    |       |             |                     |   02h = V1.1            |
    
    |       |             |                     |   03h = V1.2            |
    
    |       |             |                     |   04h = V1.3            |
    
    |       |             |                     |   05h = V1.4            |
    
    |       |             |                     |   06h = V1.5            |
    
    |       |             |                     |   07h = V1.51           |
    
    |       |             |                     |   FFh = version         |
    
    |       |             |                     |   information is        |
    
    |       |             |                     |   contained in the      |
    
    |       |             |                     |   supplemental interface|
    
    |       |             |                     |   block (SIB)           |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0443h | CARDID      | Co-processor        | = 0h-Fh                 |
    
    |       |             | adapter number set  |                         |
    
    |       |             | by system unit      |                         |
    
    |       |             | support software.   |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0444h |  MAXTASK    | Highest task number.| = 0h-F8h                |
    
    |       |             | Set by system unit  |                         |
    
    |       |             | support software.   |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0445h |  MAXPRI     | Lowest priority     | = 1h-FFh                |
    
    |       |             | level (highest      |                         |
    
    |       |             | number).  Set by    |                         |
    
    |       |             | system unit support |                         |
    
    |       |             | software.           |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0446h |  MAXQUEUE   | Highest user queue  | = 0h-FEh                |
    
    |       |             | number. Set by      |                         |
    
    |       |             | system unit support |                         |
    
    |       |             | software.           |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0447h |  MAXTIME    | High software timer | = 0h-FEh                |
    
    |       |             | number. Set by      |                         |
    
    |       |             | system unit support |                         |
    
    |       |             | software.           |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0448h-|  TCBTAB@    | 80186 logical       |                         |
    
    | 044Bh |             | address pointer to  |                         |
    
    |       |             | TCB table (TCBTAB). |                         |
    
    |       |             | Initialized by the  |                         |
    
    |       |             | Realtime Control    |                         |
    
    |       |             | Microcode.          |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 044Ch-|  PRIL@      | 80186 logical       |                         |
    
    | 044Fh |             | address pointer to  |                         |
    
    |       |             | priority list       |                         |
    
    |       |             | (PRIL). Initialized |                         |
    
    |       |             | by the Realtime     |                         |
    
    |       |             | Control Microcode.  |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0450h-|  STORPTR    | First free storage  |                         |
    
    | 0453h |             | block pointer.      |                         |
    
    |       |             | (0450h-0451h =      |                         |
    
    |       |             | segment of next free|                         |
    
    |       |             | storage block.      |                         |
    
    |       |             | 0452h-0453h =       |                         |
    
    |       |             | segment of previous |                         |
    
    |       |             | free storage block.)|                         |
    
    |       |             | 80186 logical       |                         |
    
    |       |             | address pointer to  |                         |
    
    |       |             | base memory free    |                         |
    
    |       |             | storage chain.      |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0454h-|  Reserved   | Word of 0.          |  Must be 0              |
    
    | 0455h |             |                     |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0456h-|  HCD        | Hardware Config-    | Note:                   |
    
    | 0459h |             | uration Descriptor  | See following           |
    
    |       |             | (HCD).  The HCD is  | discussion of HCD and   |
    
    |       |             | a bit specific      | Extended HCD.           |
    
    |       |             | descriptor of the   |                         |
    
    |       |             | available resources |                         |
    
    |       |             | on the co-processor |                         |
    
    |       |             | adapter.  Initial-  |                         |
    
    |       |             | ized by the         |                         |
    
    |       |             | Bootstrap Loader.   |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 045Ah-|  BCB@       | Pointer to offset of|                         |
    
    | 045Bh |             | first BCB in page   |                         |
    
    |       |             | 0 (segment 0).      |                         |
    
    |       |             | Initialized by the  |                         |
    
    |       |             | Realtime Control    |                         |
    
    |       |             | Microcode.  The     |                         |
    
    |       |             | Realtime Control    |                         |
    
    |       |             | Microcode ensures   |                         |
    
    |       |             | that its own input  |                         |
    
    |       |             | buffer, output      |                         |
    
    |       |             | buffer, and         |                         |
    
    |       |             | secondary status    |                         |
    
    |       |             | buffer are allocated|                         |
    
    |       |             | in a visible region |                         |
    
    |       |             | of memory regardless|                         |
    
    |       |             | of the page size.   |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 045Ch-|  TASKTAB@   | 80186 logical       |                         |
    
    | 045Fh |             | address pointer to  |                         |
    
    |       |             | to task table       |                         |
    
    |       |             | (TASKTAB).          |                         |
    
    |       |             | Initialized by the  |                         |
    
    |       |             | Realtime Control    |                         |
    
    |       |             | Microcode. This     |                         |
    
    |       |             | structure is not    |                         |
    
    |       |             | located in expanded |                         |
    
    |       |             | memory.             |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0460h-|  QUEUETAB@  | 80186 logical       |                         |
    
    | 0463h |             | address pointer     |                         |
    
    |       |             | to the user queue   |                         |
    
    |       |             | table (QUEUETAB).   |                         |
    
    |       |             | Initialized by the  |                         |
    
    |       |             | Realtime Control    |                         |
    
    |       |             | Microcode.          |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0464h-|  TIMETAB@   | 80186 logical       |                         |
    
    | 0467h |             | address pointer to  |                         |
    
    |       |             | the timer block     |                         |
    
    |       |             | list.  Initialized  |                         |
    
    |       |             | by the Realtime     |                         |
    
    |       |             | Control Microcode.  |                         |
    
    |       |             | These fields and    |                         |
    
    |       |             | their associated    |                         |
    
    |       |             | data structures     |                         |
    
    |       |             | reside in memory,   |                         |
    
    |       |             | which is always     |                         |
    
    |       |             | addressable.  These |                         |
    
    |       |             | structures are not  |                         |
    
    |       |             | located in          |                         |
    
    |       |             | expanded memory.    |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0468h-|  Extended   | The extended HCD    | Note:                   |
    
    | 046Bh |  HCD        | indicates the type  | See following           |
    
    |       |             | of communications   | discussion of Extended  |
    
    |       |             | chips installed on  | HCD.                    |
    
    |       |             | the adapter.        |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 046Ch-|  Extended   | The extended storage|                         |
    
    | 046Dh |  storage    | size is a 2-byte    |                         |
    
    |       |             | field which contains|                         |
    
    |       |             | the total number of |                         |
    
    |       |             | 16KB pages of stor- |                         |
    
    |       |             | age on the adapter. |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0470h-|  RESERVED3  | Reserved.           | Must be 0.              |
    
    | 0473h |             |                     |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0474h-|  SIB@       | 80186 logical       |                         |
    
    | 0477h |             | address pointer to  |                         |
    
    |       |             | the Supplemental    |                         |
    
    |       |             | Interface Block.    |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 0478h-|  STORSIZE   | Number of paragraphs|                         |
    
    | 0479h |             | of base memory on   |                         |
    
    |       |             | this co-processor   |                         |
    
    |       |             | adapter.  Initially |                         |
    
    |       |             | set by Bootstrap    |                         |
    
    |       |             | Loader.             |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 047Ah |  DB0ID      | Interface Board     |                         |
    
    |       |             | ID.                 |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 047Bh |  DB1ID      | Interface Board     |                         |
    
    |       |             | ID.                 |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    | 047Ch-|  STATARRAY  | Primary status byte | Note                    |
    
    | nnnnh |             | array.  Primary     | See following           |
    
    |       |             | status of each task | discussion of Primary   |
    
    |       |             | and Realtime Control| Status Byte.            |
    
    |       |             | Microcode.  One byte|                         |
    
    |       |             | for the Realtime    |                         |
    
    |       |             | Control Microcode   |                         |
    
    |       |             | and one byte for    |                         |
    
    |       |             | each possible task. |                         |
    
    |       |             | The size of the     |                         |
    
    |       |             | array = MAXTASK + 1.|                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    |       |             | Byte 0 (Realtime    |                         |
    
    |       |             | Control Microcode   |                         |
    
    |       |             | Status Bytes)       |                         |
    
    |       |             | initialized to 0    |                         |
    
    |       |             | by Bootstrap Loader.|                         |
    
    |       |             | All other bytes     |                         |
    
    |       |             | initialized to 0    |                         |
    
    |       |             | by the Realtime     |                         |
    
    |       |             | Control Microcode.  |                         |
    
    +-------+-------------+---------------------+-------------------------+
    
    

    Hardware Configuration Descriptor (HCD) Bit Definition

    The hardware configuration descriptor (HCD) is a doubleword at segment:offset 0:456 in the interface block. It indicates which communication ports and which CIOs are present and functioning, and it can be used to determine the number of ports available on the co-processor adapter. Note that bits 0-3 of the HCD retain their original meaning for compatibility with existing applications. These bits are set only if the corresponding SCC or CIO is present and functioning. New applications should use bits 8-31 of the HCD in conjunction with the extended HCD to determine the presence of specific hardware on the interface board. The HCD is defined in the following diagram and the extended HCD is defined on the following page.

    
    
    
                 +----+----+----+----+----+----+----+----+
    
      Bit:       | 7  | 6  | 5  | 4  | 3  | 2  | 1  | 0  |
    
                 +----+----+----+----+----+----+----+----+
    
      0:0456h    | 0  | 0  | 0  | 0  | c1 | s3 | s2 | s1 |
    
                 +----+----+----+----+----+----+----+----+
    
      0:0457h    | c7 | c6 | c5 | c4 | c3 | c2 | c1 | c0 |
    
                 +----+----+----+----+----+----+----+----+
    
      0:0458h    | s7 | s6 | s5 | s4 | s3 | s2 | s1 | s0 |
    
                 +----+----+----+----+----+----+----+----+
    
      0:0459h    | s15| s1 | s13| s12| s1 | s1 | s9 | s8 |
    
                 +----+----+----+----+----+----+----+----
    
    
    
      where:
    
         c0-c7    are individual bits indicating the presence of
    
                  CIOs 0-7.
    
                  1 = present and functioning
    
                  0 = not present or not functioning
    
         s0-s15   are individual bits indicating the presence of
    
                  SCCs (Zilog, Signetics, or others) 0-15.
    
                  1 = present and functioning
    
                  0 = not present or not functioning
    
    
    
    

    Extended HCD

    The bits in this doubleword distinguish what type of communications chips are installed. To check for presence of the hardware, the HCD should be used. In the extended HCD, zeros indicate a Zilog communications chip to remain compatible with earlier Realtime Control Microcode versions, which reserve the extended HCD field as all zeros. The extended HCD is shown in the following diagram:

    
                 +--------+---------+--------+---------+
    
      Bit:       | 7    6 | 5    4  | 3    2 | 1    0  |
    
                 +--------+---------+--------+---------+
    
      0:0468h    |   cc3  |   cc2   |  cc1   |   cc0   |
    
                 +--------+---------+--------+---------+
    
      0:0469h    |   cc7  |   cc6   |  cc5   |   cc4   |
    
                 +--------+---------+--------+---------+
    
      0:046Ah    |   cc11 |   cc10  |  cc9   |   cc8   |
    
                 +--------+---------+--------+---------+
    
      0:046Bh    |   cc15 |   cc14  |  cc13  |   cc12  |
    
                 +--------+---------+--------+---------+
    
    
    
      where
    
         cc0-cc15 are pairs of bits indicating the type of
    
                  communications chip
    
                  00 = Zilog SCC
    
                  01 = Signetics DUSCC
    
                  10 = reserved
    
                  11 = reserved
    
    

    The extended HCD indicates the type of communications chips installed on the adapter.

    Primary Status Byte Bit Definition
    
    
    
    Name     Bit   Description
    
    ----------------------------------------------------------------
    
    Load      0    Loaded.  This bit is set by the Realtime
    
                   Control Microcode when a task is loaded or
    
                   built.  It is reset when a task is unloaded.
    
    
    
    Init      1    Initialized.  This bit is set by the Realtime
    
                   Control Microcode when a task issues the
    
                   Initcomp Service Call (SVC).  It is reset when
    
                   a task is stopped.
    
    
    
    Restart/  2    For Task 0, bit on indicates that the
    
    Input          co-processor adapter is requesting a system
    
                   re-start of the system unit.  The system unit
    
                   should simulate the Ctrl+Alt+Del sequence via
    
                   software to cause the system unit to restart.
    
                   It is reset when Task 0 is initialized.
    
    
    
                   Tasks can use this bit to indicate that input
    
                   data is ready to be read by the system unit.
    
                   The use of this bit is optional and not
    
                   checked by the Realtime Control Microcode.  If
    
                   the bit is used by a task, the task is
    
                   responsible for both setting and resetting it.
    
    
    
    WATCHDOG  3    Watchdog active if on (used by the Realtime
    
                   Control Microcode only; for task,
    
                   user-definable).  It is set when the watchdog
    
                   timer is active.
    
    
    
                   Tasks can use bit 3 to indicate that the task
    
                   is ready to receive data from the system unit.
    
                   The use of this bit is optional and not
    
                   checked by the Realtime Control Microcode.  If
    
                   used by a task, it is responsible for setting
    
                   and resetting it.
    
    
    
    Name     Bit   Description
    
    ----------------------------------------------------------------
    
    ERROR     4    Bit on indicates that the task has detected an
    
                   error.  The task's secondary status should be
    
                   examined to determine the cause of the error.
    
                   This bit is reset by the Realtime Control
    
                   Microcode after receipt of a command directed
    
                   to this task from the system unit.  It is set
    
                   by the task.
    
    
    
    STATUS    5    Secondary status available.  This bit is set
    
                   by the task and is used to indicate that the
    
                   data in the task's secondary status buffer is
    
                   valid.  The bit is reset by the Realtime
    
                   Control Microcode after receipt of a command
    
                   directed to this task from the system unit.
    
    
    
    OUTPUT    6    Output buffer busy.  This bit is set by the
    
                   Realtime Control Microcode when a task
    
                   receives a command.  It indicates that the
    
                   task's output buffer should not be
    
                   overwritten.  This bit should be cleared by
    
                   the task.
    
    
    
    BUSY      7    Busy.  A task cannot receive commands from the
    
                   system unit when this bit is set.  It is set
    
                   by the Realtime Control Microcode when a task
    
                   receives a command.  This is the only
    
                   interlock-type bit that must be tested before
    
                   single-byte commands are issued.  The commands
    
                   that require parameters in the output buffer
    
                   must also check the output busy bit before the
    
                   parameters are written to the output buffer.
    
    
    
    

    Supplemental Interface Block (SIB)

    The supplemental interface block is an extension to the interface block. Its contents are initialized by both operating systems support and Realtime Control Microcode. The supplemental interface block is used by the Realtime Control Microcode.

    Purpose:
    Used as an extension to the Interface Block.

    Location:
    Pointed to by SIB@ of the Interface Block.

    Size:
    10h bytes

    Initialization:
    The Realtime Control Microcode sets the following values at Realtime Control Microcode initialization:
    The following values are set by the operating system support and programming services:

    The format of the supplemental interface block is as follows.

    
    
    
              +----------------------------------------------------------------+
    
    
    
              | Supplemental Interface Block                                   |
    
    
    
              +------------+--------------------------+------------------------+
    
    
    
     Offset   | Field Name | Description              | Comments               |
    
    
    
              +------------+--------------------------+------------------------+
    
     00h      | SIBLEN     | Length of SIB.           | Set by Realtime Control|
    
              |            |                          | Microcode.             |
    
              +------------+--------------------------+------------------------+
    
     01h      | CARDTYPE   | Adapter type             | Set by Realtime Control|
    
              |            |  80h = Portmaster        | Microcode.             |
    
              |            |        Adapter/A         |                        |
    
              |            |  00h = Multiport Adapter,|                        |
    
              |            |        Model 2           |                        |
    
              +------------+--------------------------+------------------------+
    
     02h      | PATVER     | Realtime Control         | Set by Realtime Control|
    
              |            | Microcode patch          | Microcode.             |
    
              |            | level initially 00h.     |                        |
    
              +------------+--------------------------+------------------------+
    
     03h      | MINVER     | Realtime Control         | Set by Realtime Control|
    
              |            | Microcode minor          | Microcode.             |
    
              |            | version code.  00h for   |                        |
    
              |            | Realtime Control         |                        |
    
              |            | Microcode 2.0. 01h for   |                        |
    
              |            | Realtime Control         |                        |
    
              |            | Microcode 2.01.          |                        |
    
              +------------+--------------------------+------------------------+
    
     04h      | MAJVER     | Realtime Control         | Set by Realtime Control|
    
              |            | Microcode major          | Microcode.             |
    
              |            | version code.  02h for   |                        |
    
              |            | Realtime Control         |                        |
    
              |            | Microcode 2.x.           |                        |
    
              +------------+--------------------------+------------------------+
    
     05h      | MCHOPT     | Micro Channel options    | Set by operating       |
    
              |            | bit field.  Bit 0 -      | systems support.       |
    
              |            | when set, card selected  |                        |
    
              |            | feedback is supported.   |                        |
    
              |            | Bits 1 through 7 -       |                        |
    
              |            | reserved, and must be    |                        |
    
              |            | zero.                    |                        |
    
              +------------+--------------------------+------------------------+
    
     06h-09h  | SUPPT@     | System unit peer         | Set by operating system|
    
              |            | processor table physical | support.               |
    
              |            | address pointer.         |                        |
    
              +------------+--------------------------+------------------------+
    
     0Ah      | PPTNUM     | Number of peer processor | Set by operating system|
    
              |            | table entries.           | support.               |
    
              +------------+--------------------------+------------------------+
    
     0Bh      | PROSERV    | Programming services     | Set by programming     |
    
              |            | task number.             | services when loaded.  |
    
              +------------+--------------------------+------------------------+
    
     0Ch-0Fh  | CDPPT@     | 80186 logical address    | Set by Realtime Control|
    
              |            | pointer to this card's   | Microcode.             |
    
              |            | peer processor table.    |                        |
    
              +------------+--------------------------+------------------------+
    
    

    Buffer Control Block (BCB)

    Purpose:
    Used by system unit application program, tasks, and the Realtime Control Microcode to pass data, control, and direct actions of the task. Provides pointers to data and status buffers for each task.

    Location:
    Realtime Control Microcode storage on page 0 (segment 0).

    Size:
    (MAXTASK + 1) * 16 bytes. There is one BCB for the Realtime Control Microcode and for each task as specified by MAXTASK.

    Initialization:
    Initial value set by task.

    The format of a BCB is shown in the following table.

    
    +---------------------------------------------------------------------+
    
    
    
    | Buffer Control Block                                                |
    
    
    
    +-------+-------------+----------------------------+------------------+
    
    
    
    | Byte  | Field Name  | Description                | Comments         |
    
    
    
    +-------+-------------+----------------------------+------------------+
    
    | 00h   | CMD         | Command field.  This byte  | Valid command    |
    
    |       |             | is set by system unit      | values are       |
    
    |       |             | applications and inter-    | task specific.   |
    
    |       |             | rogated by application     | See "System      |
    
    |       |             | tasks.                     | Unit Commands"   |
    
    |       |             |                            | in Volume I      |
    
    |       |             |                            | for the          |
    
    |       |             |                            | commands         |
    
    |       |             |                            | supported by     |
    
    |       |             |                            | the Realtime     |
    
    |       |             |                            | Control          |
    
    |       |             |                            | Microcode.       |
    
    +-------+-------------+----------------------------+------------------+
    
    | 01h-  | STATLNG     | Length of the task's       |                  |
    
    | 02h   |             | secondary status field.    |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    | 03h-  | STATOFF     | Offset of the secondary    |                  |
    
    | 04h   |             | status field in a page.    |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    | 05h   | STATPAG     | Page number of the         |                  |
    
    |       |             | secondary status field.    |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    | 06h-  | INLNG       | Length of the input        |                  |
    
    | 07h   |             | buffer.                    |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    | 08h-  | INOFF       | Offset of the input        |                  |
    
    | 09h   |             | buffer in a page.          |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    | 0Ah   | INPAG       | Page number of the start   |                  |
    
    |       |             | of the input buffer.       |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    | 0Bh-  | OUTLNG      | Length of the output       |                  |
    
    | 0Ch   |             | buffer.                    |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    | 0Dh-  | OUTOFF      | Offset of the output       |                  |
    
    | 0Eh   |             | buffer in a page.          |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    | 0Fh   | OUTPAG      | Page number of the start   |                  |
    
    |       |             | of the output buffer.      |                  |
    
    +-------+-------------+----------------------------+------------------+
    
    

    Notes:

    1. The Task Status, Input, and Output buffers are normally in the task load module or in acquired storage. The BCB provides a central location for various system unit applications and other tasks to locate these buffers.

    2. The pointers to the buffers are in page:offset format for more direct access from system unit applications.

    3. The terms "input" and "output" are used as viewed from the system unit. The input buffer is normally used to pass data from a task to a system unit application. The output buffer is normally used to pass data from a system unit application to a task.

    Task 0 Secondary Status Field Definition

    The location of the secondary status buffer is contained in the "status and control" pointer in the Task 0 buffer control block (BCB).

    The Task 0 secondary status field is defined in the following table. The error codes for the system unit to Task 0 commands are located in the column where byte 0 equals 02h.

    
    +---------------------------------------------------------------------+
    
    
    
    | Task 0 Secondary Status Field                                       |
    
    
    
    +-------+-------------+---------------------------+-------------------+
    
    
    
    | Byte 0| Definition  | Byte 1                    | Bytes 2 - 5       |
    
    
    
    +-------+-------------+---------------------------+-------------------+
    
    | 00h   | No error    | Undefined                 | Undefined         |
    
    +-------+-------------+---------------------------+-------------------+
    
    | 01h   | Power-on    | 01h Processor error       | Undefined         |
    
    |       | diagnostic  | 02h RAM error             | Offset and segment|
    
    |       | tests       |                           | of failing bytes. |
    
    |       | errors      |                           | (Undefined for    |
    
    |       |             |                           | Portmaster        |
    
    |       |             |                           | Adapter/A.)       |
    
    |       |             | 03h Checksum error        | Undefined         |
    
    |       |             | 04h CIO test error        | Undefined         |
    
    |       |             | 05h SCC test error        | Undefined         |
    
    |       |             | 06h Shared storage        | Undefined         |
    
    |       |             |     interface chip error  |                   |
    
    |       |             | 07h Parity check error    | Undefined         |
    
    |       |             | 08h Translate table       | Undefined         |
    
    |       |             |     error (Portmaster     |                   |
    
    |       |             |     Adapter/A only)       |                   |
    
    |       |             | 09h SIMM configuration    | Undefined         |
    
    |       |             |     error (Portmaster     |                   |
    
    |       |             |     Adapter/A only)       |                   |
    
    |       |             | 0Ah Port count error      | Undefined         |
    
    |       |             | 0Bh DMAPIC register       | Undefined         |
    
    |       |             |     test error            |                   |
    
    +-------+-------------+---------------------------+-------------------+
    
    | 02h   | System unit | 01h Non-valid command     | Undefined         |
    
    |       | application | 02h Insufficient storage  | Undefined         |
    
    |       | programs to | 03h Non-valid command data| Undefined         |
    
    |       | Task 0      | 04h Non-valid task        | Undefined         |
    
    |       | command     |     header                |                   |
    
    |       | errors      | 05h Non-valid task number | Undefined         |
    
    |       |             | 06h Task previously       | Undefined         |
    
    |       |             |     loaded                |                   |
    
    |       |             | 07h Task previously       | Undefined         |
    
    |       |             |     started               |                   |
    
    |       |             | 08h Non-valid task        | Undefined         |
    
    |       |             |     priority              |                   |
    
    |       |             | 09h Non-valid command     | Undefined         |
    
    |       |             |     sequence              |                   |
    
    |       |             | 0Ah Non-valid interface   | Undefined         |
    
    |       |             |     block data            |                   |
    
    |       |             | 0Bh Task stopped by       | Undefined         |
    
    |       |             |     debug facility        |                   |
    
    |       |             | 0Ch Task previously       | Undefined         |
    
    |       |             |     stopped or not started|                   |
    
    |       |             | 0Dh Task is permanent     | Undefined         |
    
    |       |             | 0Eh Task is not available | Undefined         |
    
    |       |             | 0Fh Name not found        | Undefined         |
    
    |       |             | 10h Non-valid adapter     | Undefined         |
    
    |       |             | 11h Resource not available| Undefined         |
    
    |       |             | 12h Peer initialization   | Undefined         |
    
    |       |             |     error                 |                   |
    
    +-------+-------------+---------------------------+-------------------+
    
    | 03h   | Non-valid   | Currently executing     | Offset:Segment      |
    
    |       | Operation   | task number             | of next             |
    
    |       | Code        |                         | sequential          |
    
    |       |             |                         | instruction         |
    
    +-------+-------------+-------------------------+---------------------+
    
    | 04h   | Parity      | Currently executing     | Offset:Segment      |
    
    |       | error       | task number             | of next             |
    
    |       |             |                         | sequential          |
    
    |       |             |                         | instruction         |
    
    +-------+-------------+-------------------------+---------------------+
    
    | 05h   | Watchdog    | Currently executing     | Offset:Segment      |
    
    |       | Timer       | task number             | of next             |
    
    |       | timed out   |                         | sequential          |
    
    |       |             |                         | instruction         |
    
    +-------+-------------+-------------------------+---------------------+
    
    | 06h   | System unit | Undefined               | Undefined           |
    
    |       | computer    |                         |                     |
    
    |       | cannot be   |                         |                     |
    
    |       | interrupted |                         |                     |
    
    +-------+-------------+-------------------------+---------------------+
    
    | 07h   | Translate   | See note below          | Undefined           |
    
    |       | table error |                         |                     |
    
    +-------+-------------+-------------------------+---------------------+
    
    | 08h   | DAC error   | See note below          | Undefined           |
    
    +-------+-------------+-------------------------+---------------------+
    
    | 09h   | External    | Undefined               | Undefined           |
    
    |       | non-maskable|                         |                     |
    
    |       | interrupt   |                         |                     |
    
    |       | error       |                         |                     |
    
    +-------+-------------+-------------------------+---------------------+
    
    | 0Ah   | Channel     | See note below          | Undefined           |
    
    |       | check error |                         |                     |
    
    +-------+-------------+-------------------------+---------------------+
    
    | FFh   | System      | Requesting task number  | Undefined           |
    
    |       | restart     |                         |                     |
    
    |       | request     |                         |                     |
    
    +-------+-------------+-------------------------+---------------------+
    
    

    Note:

    See "Asynchronous Error Handling" for additional information on Secondary Status Field values for asynchronous errors.

    Task Table (TASKTAB)

    Purpose:
    Control block to point to the task header of each task

    Location:
    Realtime Control Microcode storage

    Size:
    (MAXTASK * 2) + 2 bytes

    Initialization:
    All values initialized to 0

    The format of the TASKTAB is as follows:

    
    +---------------------------------------------------------------------+
    
    
    
    | Task Table (TASKTAB)                                                |
    
    
    
    +----------+----------+----------------------------+------------------+
    
    
    
    | Byte     | Field    | Description                | Comments         |
    
    |          | Name     |                            |                  |
    
    
    
    +----------+----------+----------------------------+------------------+
    
    | 00h-     | Task 0   | Segment value of Realtime  |                  |
    
    | 01h      |          | Control Microcode header.  |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 02h-     | Task 1   | Segment value location of  | 0 = task not     |
    
    | 03h      |          | task header for Task 1.    | loaded or built. |
    
    +----------+----------+----------------------------+------------------+
    
    | 04h-     | Task 2   | Segment value location of  | 0 = task not     |
    
    | 05h      |          | task header for Task 2.    | loaded or built. |
    
    +----------+----------+----------------------------+------------------+
    
    | .        | .        | .                          |                  |
    
    | .        | .        | .                          |                  |
    
    | .        | .        | .                          |                  |
    
    +----------+----------+----------------------------+------------------+
    
    |(MAXTASK* | Task     | Segment value location of  | 0 = task not     |
    
    | 2)       | MAXTASK  | task header for Task       | loaded or built. |
    
    |          |          | MAXTASK.                   |                  |
    
    +----------+----------+----------------------------+------------------+
    
    

    Task Control Block Table (TCBTAB)

    Purpose:
    Control block to point to TCB for each task

    Location:
    Realtime Control Microcode storage

    Size:
    (MAXTASK * 2) + 2 bytes

    Initialization:
    All values initialized to 0

    The format of the TCBTAB is as follows:

    
    +---------------------------------------------------------------------+
    
    
    
    | Task Control Block Table (TCBTAB)                                   |
    
    
    
    +----------+----------+----------------------------+------------------+
    
    
    
    | Byte     | Field    | Description                | Comments         |
    
    |          | Name     |                            |                  |
    
    
    
    +----------+----------+----------------------------+------------------+
    
    | 00h-01h  | Task 0   | Always 0 and exists only   |                  |
    
    |          |          | for ease of access into    |                  |
    
    |          |          | table.  Table entry =      |                  |
    
    |          |          | TCBTAB@ + (2 * TASKNUM).   |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 02h-03h  | Task 1   | Points to TCB of Task 1.   | 0 = task does not|
    
    |          |          |                            | exist or not     |
    
    |          |          |                            | started.         |
    
    +----------+----------+----------------------------+------------------+
    
    | 04h-05h  | Task 2   | Points to TCB of Task 2.   | 0 = task does not|
    
    |          |          |                            | exist or not     |
    
    |          |          |                            | started.         |
    
    +----------+----------+----------------------------+------------------+
    
    | .        | .        |                            |                  |
    
    | .        | .        |                            |                  |
    
    | .        | .        |                            |                  |
    
    +----------+----------+----------------------------+------------------+
    
    |(MAXTASK* | Task     | Points to TCB of Task      | 0 = task does not|
    
    |2)        | MAXTASK  | MAXTASK.                   | exist or not     |
    
    |          |          |                            | started.         |
    
    +----------+----------+----------------------------+------------------+
    
    

    Task Control Block (TCB)

    Purpose:
    Used to communicate information about the task

    Location:
    Realtime Control Microcode storage

    Size:
    14h bytes for each task TSKN, TPRI, CVECT, SSEG, and SPTR are initialized from the task header. Parent task number is set when a "child" task is built. Other values are initialized to 0.

    Initialization:
    Built from the task header as a result of the Start SVC or Start Task command.

    The format of a TCB is shown in the following table.

    
    +---------------------------------------------------------------------+
    
    
    
    | Task Control Block (TCB)                                            |
    
    
    
    +----------+----------+----------------------------+------------------+
    
    
    
    | Byte     | Field    | Description                | Comments         |
    
    |          | Name     |                            |                  |
    
    
    
    +----------+----------+----------------------------+------------------+
    
    | 00h-01h  | NEXT     | Next TCB pointer.          |                  |
    
    |          |          | Points to TCB of next      |                  |
    
    |          |          | dispatchable task in       |                  |
    
    |          |          | list.  Points to this      |                  |
    
    |          |          | TCB if only task on        |                  |
    
    |          |          | this priority.  Set by     |                  |
    
    |          |          | the Realtime Control       |                  |
    
    |          |          | Microcode.  Task must      |                  |
    
    |          |          | not modify this field.     |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 02h-03h  | PREV     | Previous TCB pointer.      |                  |
    
    |          |          | Points to previous TCB     |                  |
    
    |          |          | in list.  Points to        |                  |
    
    |          |          | this TCB if this is        |                  |
    
    |          |          | only task on this          |                  |
    
    |          |          | priority.  Set by the      |                  |
    
    |          |          | Realtime Control           |                  |
    
    |          |          | Microcode.  Task must      |                  |
    
    |          |          | not modify this field.     |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 04h      | TSKN     | Task number.  Task         | = 01h - MAXTASK  |
    
    |          |          | must not modify.           |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 05h      | TPRI     | Task priority.  Task       | = 01h - MAXPRI   |
    
    |          |          | must not modify.           |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 06h      | RETCODE  | Return code of error.      |                  |
    
    |          |          | See SVC error codes        |                  |
    
    |          |          | for descriptions.          |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 07h      | STB      | State byte.  Task          | *(see following  |
    
    |          |          | must not modify.           |   description)   |
    
    +----------+----------+----------------------------+------------------+
    
    | 08h-09h  | PSTCD    | Post code.  Indicates      | **(see following |
    
    |          |          | most recent reason why     |    description)  |
    
    |          |          | this task was posted.      |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 0Ah      | POSTFLAG | Post flag to indicate      |                  |
    
    |          |          | that task has been         |                  |
    
    |          |          | posted.  It is task's      |                  |
    
    |          |          | responsibility to          |                  |
    
    |          |          | check and clear.           |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 0Bh      | PARENT   | Parent task number.  If    | Task must not    |
    
    |          |          | this task is a parent task,| modify.          |
    
    |          |          | indicates number of        |                  |
    
    |          |          | child tasks.  Set by       |                  |
    
    |          |          | "Build" SVC and used for   |                  |
    
    |          |          | error recovery purposes.   |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 0Ch-0Dh  | CVECT    | Command vector offset.     | Task should not  |
    
    |          |          | Vector to be called when   | modify if command|
    
    |          |          | a command is received      | to that task can |
    
    |          |          | from the host computer.    | occur.           |
    
    +----------+----------+----------------------------+------------------+
    
    | 0Eh-0Fh  | CMDVEC   | Command vector segment.    | Task should not  |
    
    |          |          |                            | modify if command|
    
    |          |          |                            | to that task can |
    
    |          |          |                            | occur.           |
    
    +----------+----------+----------------------------+------------------+
    
    | 10h-11h  | SSEG     | Stack segment for this     | Task must not    |
    
    |          |          | task.                      | modify.          |
    
    |          |          |                            |                  |
    
    +----------+----------+----------------------------+------------------+
    
    | 12h-13h  | SPTR     | Stack pointer value for    | Task must not    |
    
    |          |          | this task.                 | modify.          |
    
    |          |          |                            |                  |
    
    +----------+----------+----------------------------+------------------+
    
    

    State Byte (STB) Bit Definition
    
    ----------------------------------------------------------
    
      Bit        Meaning
    
    ----------------------------------------------------------
    
      0          If 1, task is queued
    
                 If 0, task is waiting (not queued)
    
    
    
      1          If 1, task suspended
    
                 If 0, task not suspended
    
    
    
      2          If 1, task suspended by Realtime
    
                 Control Microcode
    
                 If 0, task not suspended by Realtime
    
                 Control Microcode
    
    
    
      3          If 1, task resumed by Realtime
    
                 Control Microcode
    
                 If 0, task not resumed by Realtime
    
                 Control Microcode
    
    
    
      6          If 1, task is permanent
    
                 If 0, task is not permanent
    
    
    
      7          If 1, task is a parent task
    
                 If 0, task is not a parent task
    
    

    Post Code (PSTCD) Bit Definition
    
    
    
    -----------------------------------------------------------
    
     Bit    Meaning (Suggested Only, No Data Checks Are Made)
    
    -----------------------------------------------------------
    
     0      POST.  Posted by task x.  The task ID for task is
    
            in bits 8-15 of the post code.  Bits 1-7
    
            can be used for unique user codes.
    
    
    
     1      NEWCMD.  A new command is in the command buffer.
    
    
    
     2      Timer expired
    
    
    
     3      Posted by I/O interrupt handler
    
    
    
     4-7    User defined
    
    
    
     8-15   Posting task number
    
    

    Task Header

    Purpose:
    Used to pass task's initial parameters to the Realtime Control Microcode. Built by task writer or other task.

    Location:
    At location 0 in the task load module. Task header must be in the same segment as the task's resource blocks.

    Size:
    1Ch bytes. One per task.

    Initialization:
    Initial value task defined.

    The format of a task header is as follows:

    
    +---------------------------------------------------------------------+
    
    
    
    | Task Header                                                         |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    
    
    | Byte   | Field Name  | Description                | Comments        |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    | 00h-   | TASKLNG1    | First 4 bytes = 32-bit     |                 |
    
    | 01h    |             | module length.  Read by    |                 |
    
    |        |             | loader when task is        |                 |
    
    |        |             | loaded.  Set by loader     |                 |
    
    |        |             | for .EXE files.            |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 02h-   | TASKLNG2    | Must be coded in source    |                 |
    
    | 03h    |             | file for .COM files.       |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 04h    | TASKNUM     | Task number.  Set by       |                 |
    
    |        |             | Applications Loader        |                 |
    
    |        |             | Utility or build task.     |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 05h    | Reserved    | Reserved.                  | Must be 0       |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 06h    | TASKID      | Task identification.       |                 |
    
    | 07h    |             | User-defined.              |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 08h    | TASKPRI     | Task priority.             | 1 - MAXPRI      |
    
    |        |             | User-defined.              |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 09h    | Reserved    | Reserved for               | Must be 0 when  |
    
    |        |             | co-processor adapter       | task is started |
    
    |        |             | Application Debug          |                 |
    
    |        |             | Utility use.               |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 0Ah-   | CMDOFF      | Command vector offset.     |                 |
    
    | 0Bh    |             | User-defined.  This is     |                 |
    
    |        |             | the offset of the task     |                 |
    
    |        |             | command handler            |                 |
    
    |        |             | routine.  This routine     |                 |
    
    |        |             | is called (via a           |                 |
    
    |        |             | Far Call) by the           |                 |
    
    |        |             | Realtime Control Micro-    |                 |
    
    |        |             | code when a system unit    |                 |
    
    |        |             | application presents a     |                 |
    
    |        |             | command to the task.       |                 |
    
    |        |             | Tasks should treat this    |                 |
    
    |        |             | routine as an interrupt    |                 |
    
    |        |             | handler, preserving the    |                 |
    
    |        |             | machine state and          |                 |
    
    |        |             | limiting processing,       |                 |
    
    |        |             | and return to the          |                 |
    
    |        |             | Realtime Control           |                 |
    
    |        |             | Microcode via a Far        |                 |
    
    |        |             | Return.                    |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 0Ch-   | CMDSEG      | Command vector segment.    |                 |
    
    | 0Dh    |             |                            |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 0Eh-   | INITOFF     | Initial entry vector       |                 |
    
    | 0Fh    |             | offset.  User-defined.     |                 |
    
    |        |             | This is the offset of      |                 |
    
    |        |             | the task's initial         |                 |
    
    |        |             | entry point.  The          |                 |
    
    |        |             | Realtime Control           |                 |
    
    |        |             | Microcode dispatches       |                 |
    
    |        |             | the task at this           |                 |
    
    |        |             | address when               |                 |
    
    |        |             | the task is started.       |                 |
    
    |        |             | The task executes          |                 |
    
    |        |             | here at task               |                 |
    
    |        |             | initialization time.       |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 10h-   |  INITSEG    | Initial entry vector       |                 |
    
    | 11h    |             | segment.                   |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 12h-   |  DATASEG    | Data segment value.        |                 |
    
    | 13h    |             |                            |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 14h-   |  STKSEG     | Stack segment value.       |                 |
    
    | 15h    |             |                            |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 16h-   | STKPTR      | Stack pointer value;       |                 |
    
    | 17h    |             | user-defined.              |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 18h-   | RBPTR       | Resource block chain       | Must be 0 at    |
    
    | 19h    |             | pointer.  Task must        | start time      |
    
    |        |             | not modify.                |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 1Ah-   | HRDEXT      | Extension offset.          | 0 indicates     |
    
    | 1Bh    |             | Offset within same         | no extension    |
    
    |        |             | segment header for         |                 |
    
    |        |             | user-defined header        |                 |
    
    |        |             | information.               |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 1Ch-   | TSKPARMS    | Command line parameters    |                 |
    
    | 6Bh    |             | passed by loader.          |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 6Ch-   |             | Resource block area        | The resource    |
    
    | nnh    |             | (size as required).        | blocks must be  |
    
    |        |             |                            | in the same     |
    
    |        |             |                            | segment as the  |
    
    |        |             |                            | task header.    |
    
    |        |             |                            | Although not    |
    
    |        |             |                            | required, the   |
    
    |        |             |                            | resource blocks |
    
    |        |             |                            | normally follow |
    
    |        |             |                            | the task        |
    
    |        |             |                            | header.         |
    
    +--------+-------------+----------------------------+-----------------+
    
    

    Priority Queue Scheduling

    When a task is started, its priority is established from the priority byte in its task header. This is the priority that the task is assigned for dispatch by the Realtime Control Microcode; the lower the value, the higher the priority for dispatching.

    For example, tasks at priority 2 are dispatched when there are dispatchable tasks on priorities 2 and 7. As long as there is a task dispatchable at a priority higher than Task A's priority, Task A is not dispatched. Task A may still receive interrupts because interrupts, if enabled, are a higher priority than the dispatch of tasks, but if Task A posts itself in an interrupt handler, it is not dispatched until its priority is the highest priority with dispatchable tasks. Furthermore, if a higher priority task is posted, that task is given control over Task A. The priority assigned to tasks is very important in the operation of the tasks. Higher priority tasks should relinquish control ("wait" themselves) if they do not need to be on the dispatch queue. This allows the lower priority tasks to execute.

    The Realtime Control Microcode executes a dispatch cycle when a task requests an SVC. The Realtime Control Microcode also attempts to dispatch higher priority tasks at the end of the Realtime Control Microcode's first level interrupt handlers (FLIHs), which execute when hardware interrupts are generated (referred to as preemptive dispatches). The time slice timer is one example of a hardware interrupt that can cause a preemptive dispatch cycle to occur. This timer is programmed by the Realtime Control Microcode to interrupt 10 milliseconds after the most recent dispatch.

    If a task executes a 10-millisecond code path with no SVCs, the timeslice timer expires and forces a preemptive dispatch cycle.

    Changing a task's priority in its header after it is started does not change its priority. When a task is started, a copy of the task's priority is made into the task's TCB. If the priority of a task needs to be changed, it must be changed in the TCB. This change of priority does not take effect until the task is put onto the dispatch queue. To ensure that the new priority takes effect, the task can be suspended, the priority changed in the TCB, and the task resumed. It is important that the task's priority is not changed at a time when it could be put on the dispatch queue. Instead, suspending the task prevents that from occurring.

    Task State Control

    The following diagrams describe the transitions between the various task states:

    
                 +-------------------------------------------+------------+
    
                 |     Command or Supervisor Call            | Realtime   |
    
                 |                                           | Control    |
    
                 |                                           | Microcode  |
    
                 |                                           | Action     |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | State      | Load or   | Unload   | Start   | Stop     | Dispatch   |
    
    | Comb.      | Build     |          |         |          |            |
    
    |            |           |          |         |          |            |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | Unloaded   | Loaded    | Error    | Error   | Error    | Cannot     |
    
    |            | and not   |          |         |          | happen     |
    
    |            | started   |          |         |          |            |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | Loaded     | Error     | Unloaded | Loaded  | Loaded   | Cannot     |
    
    | and not    |           |          | &       | & not    | happen     |
    
    | started    |           |          | started | started  |            |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | Loaded,    | Error     | Unloaded | Error   | Loaded   | Cannot     |
    
    | started, & |           |          |         | & not    | happen     |
    
    | waiting    |           |          |         | started  |            |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | Loaded,    | Error     | Unloaded | Error   | Loaded   | Loaded,    |
    
    | started, & |           |          |         | & not    | started,   |
    
    | posted     |           |          |         | started  | posted &   |
    
    |            |           |          |         |          | executing  |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | Loaded,    | Error     | Unloaded | Error   | Loaded   | Cannot     |
    
    | Started,   |           |          |         | & not    | happen     |
    
    | Posted, &  |           |          |         | started  |            |
    
    | Executing  |           |          |         |          |            |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | Loaded,    | Error     | Unloaded | Error   | Loaded   | Cannot     |
    
    | Started,   |           |          |         | & not    | happen     |
    
    | Posted, &  |           |          |         | started  |            |
    
    | Suspended  |           |          |         |          |            |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | Loaded,    | Error     | Unloaded | Error   | Loaded   | Cannot     |
    
    | Started,   |           |          |         | & not    | happen     |
    
    | Waiting, & |           |          |         | started  |            |
    
    | Suspended  |           |          |         |          |            |
    
    +------------+-----------+----------+---------+----------+------------+
    
    | Resident   | Loaded    | Error    | Error   | Error    | Cannot     |
    
    |            | and not   |          |         |          | happen     |
    
    |            | started   |          |         |          |            |
    
    +------------+-----------+----------+---------+----------+------------+
    
    
    
                 +-------------------------------------------+------------+
    
                 |    Supervisor Call or Service Interrupt   | Supervisor |
    
                 |                                           | Call       |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    |            | Post      | Wait    | Suspend   | Resume  | Terminate  |
    
    | State      |           |         |           |         | But Remain |
    
    | Comb.      |           |         |           |         | Resident   |
    
    | (See note) |           |         |           |         |            |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    | Unloaded   | Error     | Cannot  | Error     | Error   | Cannot     |
    
    |            |           | happen  |           |         | happen     |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    | Loaded &   | Error     | Cannot  | Error     | Error   | Cannot     |
    
    | Not        |           | happen  |           |         | Happen     |
    
    | Started    |           |         |           |         |            |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    | Loaded,    | Loaded,   | Cannot  | Loaded,   | Error   | Cannot     |
    
    | Started, & | started,  | happen  | started,  |         | happen     |
    
    | Waiting    | & posted  |         | waiting & |         |            |
    
    |            |           |         | suspended |         |            |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    | Loaded,    | No        | Cannot  | Loaded,   | Error   | Cannot     |
    
    | Started, & | Action    | happen  | started,  |         | happen     |
    
    | Posted     |           | **      | posted &  |         | (Note 1)   |
    
    |            |           |         | suspended |         |            |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    | Loaded,    | No        | Loaded, | Loaded,   | Error   | Resident   |
    
    | Started,   | action    | started | started,  |         |            |
    
    | Posted, &  |           | &       | posted &  |         |            |
    
    | Executing  |           | waiting | suspended |         |            |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    | Loaded,    | No        | Cannot  | Error     | Loaded, | Cannot     |
    
    | Started,   | action    | happen  |           | started | happen     |
    
    | Posted, &  |           |         |           | &       |            |
    
    | Suspended  |           |         |           | posted  |            |
    
    +------------+-----------+---------=-----------+---------+------------+
    
    | Loaded,    | Loaded,   | Cannot  | Error     | Loaded, | Cannot     |
    
    | Started,   | started,  | happen  |           | started | happen     |
    
    | Waiting, & | posted &  |         |           | &       |            |
    
    | Suspended  | suspended |         |           | waiting |            |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    | Resident   | Error     | Cannot  | Error     | Error   | Cannot     |
    
    |            |           | happen  |           |         | happen     |
    
    +------------+-----------+---------+-----------+---------+------------+
    
    

    Note:

    These are not proper states but are combinations of states.

    Loading a Task

    There are two ways a task is created:

    Both of these methods:

    None of these methods requires that the task header information be available. When a task is loaded by the Application Loader Utility, the task (including the header) is not actually written into the task space until after the Request Task Load command (or similar, such as Request Task Load with boundary or Request Task Load Low) is completed. If a system unit application program needs storage on the co-processor adapter, it is permissible to "LOAD" a task of the needed size and utilize the storage as necessary. The Request Task Load command allocates the storage to the task number, but the storage is not checked for valid header characteristics unless the task is started.

    Parent/Child/Peer Task Relationships

    When a co-processor adapter task performs a Build SVC, it may build either a child task or a peer task. If a child task is built, the building task is a parent task. Child tasks cannot build child tasks. There are no restrictions on a task that builds a peer except that the peer resides in acquired storage.

    The acquired storage is taken away from the building task when the peer is built and assigned to the peer task. After a peer task is built, there is no linkage by the Realtime Control Microcode between a building task and the peer task it built. This is not true of a parent and child relationship. A parent task may not be stopped or unloaded without the child task also being stopped and unloaded. If a child task identifies itself as permanent when it does its Initcomp (initialization complete) SVC, the parent task is also marked as permanent and there is no supported mechanism to change this permanent status. A child task is not marked as permanent on the basis of the parent task being permanent.

    Unloading a Task

    The specified task is unloaded from the co-processor adapter storage. If the task is not already stopped, it is stopped as described in the Stop SVC. The task's resident storage is returned to the free memory pool and the loaded bit in the task's primary status byte in the interface block is reset to 0. If any errors are detected, the command is not performed.

    Starting and Initializing a Task

    After a task is loaded or built in the co-processor adapter, it must be started before it is dispatchable.

    At "start" time, the task is given control at the initial entry point, as defined in the task's header. The task should set up its buffers and perform any other initialization necessary upon receiving control.

    A task may be started by a Start Task command or a Start SVC. Both methods:

    1. Build the TCB for the task.

    2. Create a TCBTAB entry which points to the task's TCB.

    3. Build the task's initial stack.

    4. Post the task with the initial entry point (INITENT) vector from the task header as the address to receive control when it is first executed.

    When a task initially receives control, it executes at the label designated by the initial entry point (INITENT) vector in its task header.

    The registers have the following initial values:

    
      CS = initial segment as defined by the task header
    
      IP = initial offset as defined by the task header
    
      DS = data segment value from the task header
    
      SS = stack segment value from the task header
    
      SP = stack pointer value from the task header
    
           (to word boundary)
    
      ES = segment of task header
    
      Flags   Interrupt flag    = 1 (enabled)
    
              Carry flag        = 0
    
              Parity            = 0
    
              Sign              = 0
    
              Direction flag    = 0
    
              Trap              = 0
    
              Overflow          = 0
    
              Zero              = 0
    
              Auxiliary carry   = 0
    
    

    AX, BX, CX, DX, SI, DI, and BP are all set to the values defined for the user's stack when the stack area is reserved by the task writer.

    Starting a task does not set the "initialized" bit in its primary status byte; this is done by the Initcomp SVC. After a task has completed initialization, it should use the Initcomp SVC and "wait" itself.

    It is expected that when the task receives control the first time, it:

    1. Acquires the necessary resources. (This is a recommendation only. In other cases, it may be more appropriate to acquire resources only as they are needed.)

    2. Initializes its BCB.

    3. Does other required initial setup.

    4. Does an Initcomp (initialization complete) SVC, which marks the task as initialized. The task can receive commands from the system unit. A task that is not initialized may not receive system unit commands. However, the task can be posted, waited, suspended, resumed, interrupted, and request SVCs and other services from the Realtime Control Microcode.

    Permanent Task Status

    A task can mark itself as permanent, via the Initcomp SVC. Permanent classification is determined during the first Initcomp SVC. Further initialization complete SVCs are rejected with a "no-operation" error. If the task needs to be permanent and not receive commands from the system unit, it may set the busy bit in its primary status byte and, after the Initcomp SVC, leave the busy bit set to 1. If a child task requests a permanent status, its parent task is also marked as permanent. No notification is made to the parent task.

    Stopping a Task

    A task that is stopped has no TCBTAB entry, but still has an entry in the TASKTAB. It can no longer be put on the dispatch queue. The task may be restarted by a system unit program or another task. The stopped and loaded states are actually the same state. When a task is stopped, all its acquired resources are relinquished and any child tasks are stopped and unloaded. The initialized bit in the task's primary status byte is reset. If the task has a permanent status, any stop request is rejected.

    Waiting Task

    Whenever a task is idle, it should place itself in an idle or wait state. It is now ready for another task or system unit application to request its services. This request can be made through a Post SVC or POSTI service interrupt, which set the posted flag (POSTED) in the task's TCB. Before a task attempts to "wait" itself, it should first check the posted flag (POSTED) in its TCB. The posted flag must be cleared to 0 by the task or the wait request is a "no-operation."

    Posting a Task

    Posting a task puts the task on the dispatch queue.

    The task's TCB is modified as follows:

    1. The post code (PSTCD) is overwritten with the post code from the Post SVC or POSTI service interrupt.

    2. The state byte (STB) queued bit is set.

    3. The posted flag (POSTED) is set to non-0 to indicate that a service is being requested.

    The task's POST handler should follow the code that issues the Wait SVC. When the task is dispatched again, it is given control at the code immediately following the Wait SVC.

    The Post handler should reset the posted flag to 0 so that subsequent waits are not be no-operations.

    Post puts a task in the dispatch queue if it was waiting and not suspended.

    Dispatching a Task

    A dispatchable task has been posted on the dispatch queue and is dispatched to execute when it has the highest dispatchable priority or its turn comes on round-robin dispatching.

    A task that is executing is in actual control of the co-processor adapter.

    The task's I/O interrupt handlers are entered via interrupt vectors for the I/O and operate asynchronously to the mainline task code; consequently, interrupt handlers are not dispatched but receive control when the interrupt occurs (assuming interrupts are enabled and not masked).

    Suspending a Task

    Suspending a task unconditionally removes the task from the dispatch queue. The "suspended" flag in the task's state byte in the TCB is set to 1. To take a task out of the suspended state, the task is "resumed" via the Resume SVC or the RESUMEI service interrupt.

    If the suspended task is posted, it is not put on the dispatch queue until it is resumed.

    Resuming a Task

    Resuming a task cancels the suspended state of a task and resets the suspend flag in the task's state byte (in the task's TCB). If the queued flag in the task's State Byte (in the task's TCB) is on, resuming a task causes it to be put on the dispatch queue.

    The following diagram shows the progression of a typical task through various states.

    
                                  TASK STATE DIAGRAM
    
                                  ------------------
    
         +---+                  +---+                  +---+
    
         | 1 |==> Started       | 2 |==> Suspend       | 3 |==> Resume
    
         +---+                  +---+                  +---+
    
    
    
         +---+                  +---+                  +---+
    
         | 4 |==> Preempt       | 5 |==> Dispatch      | 6 |==> Stayres
    
         +---+                  +---+                  +---+
    
    
    
                                +---+
    
                                |   |==> Defined states
    
                                +---+
    
    
    
             +------+                                                +---------+
    
      +------+>Wait>+------------------------------------------------+ Loaded, |
    
      |      +------+                  +------+                      | Started,|
    
      |                             +--+<Post<+----------------------+ and     |
    
      |                             |  +------+                      | Waiting |
    
      |                             |                +---------------+-----+-+-+
    
      |                             |                |                     | |
    
      |                             |                |               +---+ | |
    
    +-------------+                 |                |               |>3>+-+ |
    
    | |           |                 |                |               +-+-+   |
    
    | |       +---+--+              |             +--+---+             |     |
    
    | |    +--+<Stop<+----------------------------+<Stop<+-----------+ |   +-+-+
    
    | |    |  +---+--+              |             +--+---+           | | +-+<2<|
    
    | |    |      +-------------+   |                |               | | | +---+
    
    | |    |                    |   |                |               | | |
    
    | |   ++----------+ +---+ +-+---+---+ +---+ +----+----+ +------+ +-+-+-----+
    
    | | +-+Loaded and +-+>1>+-+ Loaded, +-+>2>+-+ Loaded, +-+<Post<+-+ Loaded  |
    
    | | | |not Started| +---+ | Started,| +---+ | Started,| +------+ | Started |
    
    | | | +---------+-+       | and     |       | Posted, |          | Waiting |
    
    | | |           |     +---+ Posted  | +---+ | and     |          | and     |
    
    | | |           +---+ | +-+         +-+<3<+-+Suspended|          |Suspended|
    
    | | |+------------+ | | | +-+------++ +---+ |         +------+   |         |
    
    | | ||>Load,Build>+-+ | |   |      |        +-----+-+++      |   +---+-----+
    
    | | |+-----+------+   | |   |      |  +---+       | ||  +----+-+     |
    
    | | |      |          | | +-+---+  +--+>6>+-----+ | |+--+<Post<|     |
    
    | | |      |          | | |<<5>>+-+   +---+     | | |   +------+     |
    
    | | | +----+---+      | | +-----+ |             | | |                |
    
    | | | |Unloaded+-+    | |         |             | | |                |
    
    | | | +--------+ |    | | +---+   |  +--------+ | | |                |
    
    | | |            |    | +-+<4<+-+ |  |Resident+-+ | |                |
    
    | | | +--------+ |    |   +---+ | |  +--------+ | | |                |
    
    | | +-+>Unload>+-+    |         | |             | | |                |
    
    | |   +----+-+-+      |   +-----+-+-+  +---+    | | |                |
    
    | |        | +--------+   |         +--+>6>+----+ | |                |
    
    | |        |              | Loaded, |  +---+      | |                |
    
    | |        |   +------+   | Started,|             | |                |
    
    | +------------+<Wait<+---+ Posted, |             | |                |
    
    |          |   +------+   | and     | +---------+ | |                |
    
    | +------+ |              |Executing+-+>Suspend>+-+ |                |
    
    +-+<Stop<+----------------+         | +---------+   |                |
    
      +------+ |              +----+----+               |                |
    
               |                   |                    |                |
    
               |              +----+---+          +-----+--+             |
    
               +--------------+<Unload<+----------+<Unload<+-------------+
    
                              +--------+          +--------+
    
    

    Associated Interface Modules

    The following interface modules are related to task management:

    
    
    
    -----------------------------------------------
    
     Type            Invocation      Name
    
    -----------------------------------------------
    
     SVC             AH = 38h,       UNLOAD
    
                     INT = 56h
    
    
    
     SVC             AH = 39h,       BUILD
    
                     INT = 56h
    
    
    
     SVC             AH = 3Ah,       START
    
                     INT = 56h
    
    
    
     SVC             AH = 3Bh,       STOP
    
                     INT = 56h
    
    
    
     SVC             AH = 3Ch,       WAIT
    
                     INT = 56h
    
    
    
     SVC             AH = 3Dh,       SUSPEND
    
                     INT = 56h
    
    
    
     SVC             AH = 3Eh,       RESUME
    
                     INT = 56h
    
    
    
     SVC             AH = 3Fh,       POST
    
                     INT = 56h
    
    
    
     SVC             AH = 40h,       ASAP
    
                     INT = 56h
    
    
    
     SVC             AH = 41h,       STAYRES
    
                     INT = 56h
    
    
    
     SVC             AH = 48h,       INITCOMP
    
                     INT = 56h
    
    
    
     Service         INT 64h         POSTI
    
     Interrupt
    
    
    
     Service         INT 66h         RESUMEI
    
     Interrupt
    
    

    Resource Blocks

    The Realtime Control Microcode manages the various resources of the co-processor adapter. An application task requests temporary ownership of a resource via Alloc SVC 46h (allocate resource). If the resource is available, the Realtime Control Microcode assigns temporary ownership of it to the task which must follow certain rules regarding the use of the resource. The task is responsible for returning ownership of the resource to the Realtime Control Microcode via Return SVC 47h deallocate resource).

    Resources that may be acquired by application tasks are as follows:

    Resource Block Definition

    The resource block is used by the application task to request (allocate), temporarily own, and return (deallocate) use of a given co-processor adapter resource. Each request for temporary ownership of a resource requires a resource block.

    Resource blocks must be defined with these considerations:

    User Interface Rules

    Rules for resource management that an application task must follow are as follows:

    Each of the following co-processor adapter resources is discussed separately in this section:

    
    -------------------------------------------
    
                              Block
    
                              Descriptor
    
     Resource                 Value
    
    -------------------------------------------
    
     User-requestable
    
     interrupt vectors        01h
    
    
    
     RAM storage              02h
    
    
    
     DMA channels             04h
    
    
    
     User queues              05h
    
    
    
     Hardware timers          06h
    
    
    
     Software timers          07h
    
    
    
     SCC ports                09h
    
    
    
     CIO ports                0Ah
    
    
    
     Communications ports     0Ch
    
    
    
     Expanded memory pages    0Dh
    
    
    
     Extended service hooks   0Eh
    
    

    Note:

    SCC/CIO port packages (03h), RS-232 ports (08h), and RS-422 ports (0Bh) are not supported in Realtime Control Microcode 2.x.

    User-Requestable Interrupt Vectors (01h)

    There are 50 allocatable interrupt vectors. The co-processor adapter hardware uses all interrupts below 20h. The Realtime Control Microcode uses all even-numbered vectors 20h-FEh. Odd vectors 71h-BDh and EBh-FFh are resources to be used by an application task. Certain of these vectors have special meanings. The interrupt vector table assignments are shown under Chapter 13. "Interrupt Vector Table Map for the Portmaster Adapter/A and Multiport Adapter, Model 2".

    A task may request any of the odd interrupt vectors between 71h-BDh and EBh-FFh. The requests are limited only by the storage available for resource blocks in the task header segment. It is permissible to request the same interrupt vector more than once, because each interrupt vector may have multiple owners, provided that a different interrupt vector resource block is used with each request.

    When one of the user-requestable interrupts occurs, the Realtime Control Microcode receives control and, if the vector is owned by a task, passes control to the last task that requested this interrupt vector. Control is passed by a doubleword jump through the task's resource block.

    After the task has completed processing the interrupt, it should do a doubleword jump through the old vector in its own resource block, which takes it to the next most-recent requestor of this resource or, at completion, to the Realtime Control Microcode's first-level interrupt handler. The least-recent requestor returns control to the Realtime Control Microcode's first-level interrupt handler if each task passes control correctly. The Realtime Control Microcode completes the interrupt handling and returns control to the task that was interrupted.

    The Realtime Control Microcode's first-level interrupt handler requires the use of registers BX, SI, and DS. Those registers may not be used for passing parameters. The Realtime Control Microcode also uses three words of stack space prior to passing control to the first task.

    User-Requestable Interrupt Vector Resource Block

    The vector resource block (VECRB) for a user-requestable vector is shown in the table that follows:

    Purpose:
    Used to allocate and return user-requestable interrupt vectors

    Location:
    Task header segment in task storage

    Size:
    1Ch bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------------+
    
    
    
    | User-Requestable Interrupt Vector Resource Block                    |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    
    
    | Byte   | Field Name  | Description                | Comments        |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    | 00h-   | NEXT        | Pointer to next in list;   |                 |
    
    | 01h    |             | set by the Realtime        |                 |
    
    |        |             | Control Microcode.         |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 02h-   | PREV        | Pointer to previous        |                 |
    
    | 03h    |             | block in list; set by      |                 |
    
    |        |             | the Realtime Control       |                 |
    
    |        |             | Microcode.                 |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 04h    | 01h         | Block descriptor.          | = 01h           |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 05h    | VECTOR      | Interrupt vector number.   | Must be above   |
    
    |        |             |                            | 20h and odd     |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 06h    | VECTSK      | Owner task number of this  |                 |
    
    |        |             | block.                     |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 07h    | Reserved    | Reserved.                  | Must be 0       |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 08h-   | NEWOFF      | Offset for new vector.     |                 |
    
    | 09h    |             |                            |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 0Ah-   | NEWSEG      | Segment for new vector.    |                 |
    
    | 0Bh    |             |                            |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 0Ch-   | OLDVEC      | Old vector offset:         |                 |
    
    | 0Fh    |             | segment; set by the        |                 |
    
    |        |             | Realtime Control           |                 |
    
    |        |             | Microcode.                 |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 10h-   | QUICKVEC    | Quick vector value;        |                 |
    
    | 13h    |             | set by the Realtime        |                 |
    
    |        |             | Control Microcode.         |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 14h-   | Reserved    | Set and used by the        |                 |
    
    | 1Bh    |             | Realtime Control           |                 |
    
    |        |             | Microcode to link other    |                 |
    
    |        |             | tasks sharing the same     |                 |
    
    |        |             | interrupt vector.          |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    

    User-Requested Interrupt Vector Resource Block Definition

    The task must initialize the following fields in the resource block before the allocation request is made:

    
      01h        Resource block descriptor
    
      VECTOR     Interrupt vector number
    
      VECTSK     Owner task number
    
      NEWOFF     Offset for new vector
    
      NEWSEG     Segment for new vector
    
    

    The Realtime Control Microcode completes the following fields in the resource block following successful allocation of the resource to the application task:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      OLDVEC     Old vector offset:segment
    
      QUICKVEC   Quick vector value
    
    

    Allocation of User-Requestable Interrupt Vectors

    SVC 46h is used to allocate use of a particular interrupt vector to the requesting application task.

    Ownership of a User-Requestable Interrupt Vectors

    Deallocation of User-Requestable Interrupt Vectors

    SVC 47h is used to return or deallocate ownership of the same interrupt vector to the Realtime Control Microcode.

    Associated Interface Modules

    None.

    Random Access Memory (RAM) Storage (02h)

    Co-processor adapters can contain 512KB or 960KB of base RAM. (Realtime Control Microcode Version 2.01 considers a 1MB Portmaster Adapter/A to have 992KB of base RAM.) Blocks of storage may be allocated to application tasks. These blocks are allocated in paragraph (16 byte) multiples, can be requested to start on specified boundaries, and can be allocated from high or low storage.

    This resource block can only be used to allocate 80186 addressable memory (base memory).

    RAM Storage Resource Block

    The RAM Storage Resource Block (STRRB) is defined in the table that follows:

    Purpose:
    Used to allocate and return RAM storage blocks

    Location:
    Task header segment in task storage

    Size:
    16 bytes per block

    Initialization:
    Initial values set by task

    Note:

    For information on Reserved RAM for Interface Board Usage, see Page .
    
    +---------------------------------------------------------------------+
    
    
    
    | RAM Storage Resource Block                                          |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    
    
    | Byte   | Field Name  | Description                | Comments        |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    | 00h-   | NEXT        | Pointer to next block in   |                 |
    
    | 01h    |             | list; set by the Realtime  |                 |
    
    |        |             | Control Microcode.         |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 02h-   | PREV        | Pointer to previous        |                 |
    
    | 03h    |             | block in list; set by      |                 |
    
    |        |             | the Realtime Control       |                 |
    
    |        |             | Microcode.                 |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 04h    | 02h         | Block descriptor.          | = 02h           |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 05h    | HIGHLOW     | High or low storage.       | 0 = Low storage |
    
    |        |             |                            | Non-0 = High    |
    
    |        |             |                            | storage request |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 06h    | STRTSK      | Owner task number of       |                 |
    
    |        |             | this block.                |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 07h    | Reserved    | Reserved.                  | Must be 0       |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 08h-   | STRBND      | Requested storage boundary | Must be a       |
    
    | 09h    |             | in paragraphs.             | power of 2      |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 0Ah-   | STRSIZE     | Storage size of requested  |                 |
    
    | 0Bh    |             | block in paragraphs        |                 |
    
    |        |             | (16-byte increments).      |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 0Ch-   | STRSEG      | Segment of storage block;  |                 |
    
    | 0Dh    |             | set by the Realtime        |                 |
    
    |        |             | Control Microcode.         |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 0Eh-   | PARTIAL     | Partial return size in     |                 |
    
    | 0Fh    |             | paragraphs.                |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    

    RAM Storage Resource Block Definition

    The task must initialize the following fields in the resource block before the allocation request is made:

    
      02h        Resource Block descriptor
    
      HIGHLOW    High/low storage flag
    
      STRTSK     Owner task number
    
      STRBND     Requested storage boundary
    
      STRSIZE    Requested storage size
    
    

    The following fields in the resource block are completed by the Realtime Control Microcode following the allocation request by the task:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      STRSEG     Block segment of storage block
    
      PARTIAL    Partial return size
    
    

    The PARTIAL field is an exception to the rule not to modify a resource block between allocation and deallocation. Refer to "Deallocation of RAM Storage" in this section for further details.

    Allocation of RAM Storage

    Ownership of RAM Storage

    If a task owns storage that other tasks are using and the owner task is stopped, the storage should not be accessed by the other tasks. For this reason, when a parent task is stopped, all of the child tasks of that task are also stopped.

    Deallocation of RAM Storage

    Associated Interface Modules

    
    -----------------------------------------------------
    
     Type            Invocation      Name
    
    -----------------------------------------------------
    
     Diagnostic      AH = 00h,       RAM TEST
    
     test            INT FEh
    
    
    
     Diagnostic      AH = 01h,       CHECKSUM TEST
    
     test            INT FEh
    
    
    
     Diagnostic      AH = 0Fh,       RAM TEST EXTENDED
    
     test            INT FEh
    
    

    DMA Channels (04h)

    There are two DMA channels located on the 80186 processor. A task may request either or both (one at a time) DMA channels.

    The DMA channel resource block is supported only for the two 80186 DMA channels. Note, however, that these DMAs can be used for memory-to-memory transfers within a Portmaster Adapter/A or Multiport Adapter, Model 2 adapter. The 80186 DMA channels can only be used to access 80186 logical memory.

    DMA Channel Resource Block

    The DMA Channel Resource Block (DMARB) is defined in the table that follows:

    Purpose:
    Used to allocate and return a DMA channel

    Location:
    Task header segment of task storage

    Size:
    0Eh bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------------+
    
    
    
    | DMA Channel Resource Block                                          |
    
    
    
    +--------+-------------+-----------------------------+----------------+
    
    
    
    | Byte   | Field Name  | Description                 | Comments       |
    
    
    
    +--------+-------------+-----------------------------+----------------+
    
    | 00h-   | NEXT        | Pointer to next block in    |                |
    
    | 01h    |             | list; set by the Realtime   |                |
    
    |        |             | Control Microcode.          |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 02h-   | PREV        | Pointer to previous block   |                |
    
    | 03h    |             | in list; set by the         |                |
    
    |        |             | Realtime Control Microcode. |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 04h    | 04h         | Block descriptor.           | = 04h          |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 05h    | DMANUM      | DMA channel number.         | = 0 or 1       |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 06h    | DMATSK      | Owner task number of this   |                |
    
    |        |             | block.                      |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 07h    | Reserved    | Reserved.                   | Must be 0.     |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 08h-   | DMAOFF      | Offset to interrupt         |                |
    
    | 09h    |             | vector for DMA terminal     |                |
    
    |        |             | count.                      |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 0Ah-   | DMASEG      | Segment to DMA terminal     |                |
    
    | 0Bh-   |             | count interrupt vector.     |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 0Ch-   | DMABASE     | DMA base address.           | Set by the     |
    
    | 0Dh-   |             |                             | Realtime       |
    
    |        |             |                             | Control        |
    
    |        |             |                             | Microcode.     |
    
    +--------+-------------+-----------------------------+----------------+
    
    

    DMA Channel Resource Block Definition

    It is the task's responsibility to define the following fields in the resource block before the allocation request is made:

    
      04h        Resource block descriptor
    
      DMANUM     DMA channel number
    
      DMATSK     Owner task number
    
      DMAOFF     Offset to interrupt vector for DMA terminal
    
                 count
    
      DMASEG     Segment to interrupt vector
    
    

    The Realtime Control Microcode completes the following fields in the resource block when the allocation call is completed successfully:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      DMABASE    DMA base address
    
    

    Allocation of DMA Channels

    SVC 46h is invoked by the application task to obtain temporary ownership of the DMA channels.

    Ownership of DMA Channels

    No special rules apply to the use of DMA channel resources.

    Interrupt Handling

    Deallocation of DMA Channels

    SVC 47h is invoked by the application task to release ownership of DMA channels.

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    INT ACh         DMASUPPORT
    
    
    
     PROM Service    INT AEh         DMAREGS
    
    
    
     PROM Service    INT B0h         DMASTOP
    
    
    
     PROM Service    INT B2h         DMAADDR
    
    
    
     Diagnostic      AH = 0Ah,       CONFIGURE
    
     Test            INT = FEh       DMA CHANNEL
    
    

    User Queues (05h)

    The user queue is the basic method of inter-task communication. There may be up to 255 user queues. The maximum number of user queues assigned to a co-processor adapter is controlled by MAXQUEUE defined in the ICAPARM.PRM file. This value resides at 0446h in the interface block. The maximum number of user queues that a task may request is MAXQUEUE+1. The actual queue bodies are called "user queue elements", and reside in the user task's storage area.

    To allow queueing of expanded memory, the underlying structure of queues was changed with Realtime Control Microcode Version 2.0. Applications that access the queue table directly or traverse a queue will no longer work. Applications that remain above the ADDQUEUE, REMQUEUE, and RECQUEUE SVIs are protected from these changes and will continue to work unmodified.

    User Queue Resource Block

    The user queue resource block (QEURB) is defined in the table that follows:

    Purpose:
    Used to allocate and return user queues

    Location:
    Task header segment in task storage

    Size:
    08h bytes per block

    Initialization:
    Initial values set by task
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | User Queue Resource Block                                           |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    
    
    | Byte   | Field Name  | Description                | Comments        |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    | 00h-   | NEXT        | Pointer to next block in   |                 |
    
    | 01h    |             | list; set by the Realtime  |                 |
    
    |        |             | Control Microcode.         |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 02h-   | PREV        | Pointer to previous block  |                 |
    
    | 03h    |             | in list; set by the        |                 |
    
    |        |             | Realtime Control Microcode.|                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 04h    | 05h         | Block descriptor.          | = 05h           |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 05h    | QUENUM      | User queue number.         | = 0h - MAXQUEUE |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 06h    | QUETSK      | Owner task number of this  |                 |
    
    |        |             | block.                     |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 07h    | Reserved    | Reserved.                  | Must be 0       |
    
    +--------+-------------+----------------------------+-----------------+
    
    

    User Queue Resource Block Definition

    The task must complete the following fields in the resource block prior to the allocation request:

    
      05h        Resource block descriptor
    
      QUENUM     Queue number
    
      QUETSK     Owner task number
    
    

    The Realtime Control Microcode, upon allocation, completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
    

    Allocation of User Queues

    Temporary ownership of one or more user queues is obtained via SVC 46h.

    Ownership of User Queues

    
    +---------------------------------------------------------------------+
    
    
    
    | User Queues                                                         |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    
    
    | Byte   | Field Name  | Description                | Comments        |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    | 00h-   | Address of  | 32-bit physical address    | = 0 indicates   |
    
    | 03h    | next        | of next element in queue.  | this is the     |
    
    |        | element     |                            | last element    |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 04h    |                                                            |
    
    +--------+                                                            |
    
    |  .     |                                                            |
    
    |  .     |                                                            |
    
    |  .     |                                                            |
    
    |  .     |                                                            |
    
    +--------+       User-defined data for user-defined length.           |
    
    |  .     |                                                            |
    
    |  .     |                                                            |
    
    |  .     |                                                            |
    
    |  .     |                                                            |
    
    +--------+                                                            |
    
    | nh     |                                                            |
    
    +--------+------------------------------------------------------------+
    
    

    Deallocation of User Queues

    Release of a user queue is performed via the SVC 47h.

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     Service         INT 6Ah         RECQUEUE
    
     Interrupt
    
    
    
     Service         INT 6Ch         ADDQUEUE
    
     Interrupt
    
    
    
     Service         INT 6Eh         REMQUEUE
    
     Interrupt
    
    
    
     Service         INT 72h         PHYSICAL
    
     Interrupt                       ADDQUEUE
    
    

    Hardware Timers (06h)

    Four CIO hardware timers are available for use by application tasks located on the Multiport Model 2 adapter and on the Portmaster Adapter/A. The hardware timers have a granularity of 543 nanoseconds, providing a delay range from 543 nanoseconds to 35 milliseconds. These timers are used by tasks with precise timing requirements. If a task's timing requirements are satisfied by minimum time-outs in multiples of 5 milliseconds, it is more appropriate for the task to acquire a software timer. Software timers are described in detail in this chapter. For example, a task that wants to report an error if an event does not occur within 100 milliseconds, should use a software timer because the error still exists if the task is not notified until 101 milliseconds. However, if a task wants to perform an event precisely every 3 milliseconds, a hardware timer is required.

    Under Realtime Control Microcode, additional timers on any additional CIOs as defined in the Interface Board ROS are allocatable via this resource block.

    The hardware timer resource block contains an additional field not used in previous Realtime Control Microcode versions. This field is the release interrupt address for the CIO. It is set by Realtime Control Microcode. The address contained in this field must be written by the owning task's hardware timer interrupt handler to re-enable interrupts from lower or equal priority devices.

    Hardware Timer Resource Block

    The format of the hardware timer resource block (HTIMRB) is as follows:

    Purpose:
    Used to allocate and return one of the CIO hardware timers

    Location:
    Task header segment in task storage

    Size:
    10h bytes per block

    Initialization:
    Initial values set by task
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | Hardware Timer Resource Block                                       |
    
    
    
    +--------+-------------+-----------------------------+----------------+
    
    
    
    | Byte   | Field Name  | Description                 | Comments       |
    
    
    
    +--------+-------------+-----------------------------+----------------+
    
    | 00h-   | NEXT        | Pointer to next block in    |                |
    
    | 01h    |             | list; set by Realtime       |                |
    
    |        |             | Control Microcode.          |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 02h-   | PREV        | Pointer to previous block   |                |
    
    | 03h    |             | in list; set by Realtime    |                |
    
    |        |             | Control Microcode.          |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 04h    |  06h        | Block descriptor.           | = 06h          |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 05h    | HTIMNUM     | Hardware timer number.      |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 06h    | HTIMTSK     | Owner task number of this   |                |
    
    |        |             | block.                      |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 07h    | Reserved    | Reserved.                   | Must be 0.     |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 08h-   | HTIMOFF     | Interrupt vector offset     |                |
    
    | 09h    |             | for hardware timer          |                |
    
    |        |             | interrupt.                  |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 0Ah-   | HTIMSEG     | Interrupt vector segment    |                |
    
    | 0Bh    |             | for hardware timer          |                |
    
    |        |             | interrupt.                  |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 0Ch-   | HTIMBASE    | Hardware timer base         |                |
    
    | 0Dh    |             | address; set by Realtime    |                |
    
    |        |             | Control Microcode.          |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    | 0Eh-   | HWTIMREL    | Hardware timer release      |                |
    
    | 0Fh    |             | interrupt address;          |                |
    
    |        |             | set by Realtime             |                |
    
    |        |             | Control Microcode.          |                |
    
    +--------+-------------+-----------------------------+----------------+
    
    

    Hardware Timer Resource Block Definition

    The application task must complete the following fields in the resource block before the allocation request is made:

    
      06h        Resource block descriptor
    
      HTIMNUM    Hardware timer number
    
      HTIMTSK    Owner task number
    
      HTIMOFF    Offset address to timer interrupt handler
    
                 vector
    
      HTIMSEG    Segment address to timer interrupt handler
    
                 vector.
    
    

    The Realtime Control Microcode completes the following fields in the resource block when allocation of ownership is made:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      HTIMBAS    Base I/O address of timer
    
      HTIMREL    Timer releases interrupt address
    
    

    Allocation of Hardware Timers

    Allocation of a hardware timer to an application is performed through a call to SVC 46h.

    Ownership of Hardware Timers

    Deallocation of Hardware Timers

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    INT A8h         CIOTMR
    
    
    
     Diagnostic      AH = 0Bh,       CONFIGURE
    
     test            INT = FEh       HARDWARE
    
                                     TIMER
    
    

    Software Timers (07h)

    There are up to 255 software timers. The actual number of software timers assigned to a co-processor adapter is the value of MAXTIME +1 at offset 0447h in the interface block. MAXTIME is originally defined in the ICAPARM.PRM file.

    Timers are either "single-shot" (one-shot) timers or periodic timers. The increment value of a software timer is 5 milliseconds. The range is 5 milliseconds through 327.675 seconds. CPU timer 0 is used for the software timers, which are used to notify a task that a minimum of the requested time-out has occurred. These time-outs are reasonably accurate, but the task should not depend on them for exact timing measurements. Time-out requests for the software timers are made for the number of 5 millisecond intervals that the task needs. A task requesting a time-out of 3 is notified after 15 milliseconds; a task requesting a time-out of 10 is notified after 50 milliseconds.

    Software Timer Resource Block

    The following table represents the format of the software timer resource block (STIMRB):

    Purpose:
    Used to allocate and return one of the software timers

    Location:
    Task header segment in task storage

    Size:
    08h bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------------+
    
    
    
    | Software Timer Resource Block                                       |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    
    
    | Byte   | Field Name  | Description                | Comments        |
    
    
    
    +--------+-------------+----------------------------+-----------------+
    
    | 00h-   | NEXT        | Pointer to next block in   |                 |
    
    | 01h    |             | list; set by Realtime      |                 |
    
    |        |             | Control Microcode.         |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 02h-   | PREV        | Pointer to previous        |                 |
    
    | 03h    |             | block in list; set by      |                 |
    
    |        |             | Realtime Control Microcode.|                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 04h    | 07h         | Block descriptor.          | = 07h           |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 05h    | STIMNUM     | Software timer number.     | = 0 to MAXTIME  |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 06h    | STIMTSK     | Owner task number of this  |                 |
    
    |        |             | block.                     |                 |
    
    +--------+-------------+----------------------------+-----------------+
    
    | 07h    | Reserved    | Reserved.                  | Must be 0       |
    
    +--------+-------------+----------------------------+-----------------+
    
    

    Software Timer Resource Block Definition

    Upon request for allocation of a software timer, the application task should have completed the following fields in the resource block:

    
      07h        Resource block descriptor
    
      STIMNUM    Software timer number
    
      STIMTSK    Owner task number
    
    

    The Realtime Control Microcode completes the following fields in the resource block after allocation is performed:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
    

    None of these fields should be altered between allocation and return.

    Allocation of Software Timers

    Temporary ownership of a software timer is obtained through a call to SVC 46h.

    Ownership of Software Timers

    Deallocation of Software Timers

    Release of software timers is accomplished via a call to SVC 47h.

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     SVC             AH = 43h,       TIMERP
    
                     INT = 56h
    
    
    
     SVC             AH = 44h,       TIMER
    
                     INT = 56h
    
    
    
     SVC             AH = 45h,       CANCEL
    
                     INT = 56h
    
    
    
     Service         INT 68h         CANCELI
    
     Interrupt
    
    

    SCC Ports (09h)

    The SCC port resource consists of one SCC port with no associated CIO control lines and no DMA channels. This resource type should be allocated only when the communications port type is too restrictive. This resource type is provided to allow dedicated software systems or communication subsystems access to the primitive hardware resource. Valid SCC ports are 0-3 or 0-7 on a Multiport Adapter, Model 2 or a Portmaster Adapter/A, respectively.

    SCC Port Resource Block

    The SCC port resource block (SCCPRB) is defined in the table that follows:

    Purpose:
    Used to allocate and return an SCC port

    Location:
    Task header segment in task storage

    Size:
    1Ch bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------------+
    
    
    
    | SCC Port Resource Block                                             |
    
    
    
    +--------+-------------+---------------------------+------------------+
    
    
    
    | Byte   | Field Name  | Description               | Comments         |
    
    
    
    +--------+-------------+---------------------------+------------------+
    
    | 00h-   | NEXT        | Pointer to next resource  | Set by the       |
    
    | 01h    |             | block.                    | Realtime Control |
    
    |        |             |                           | Microcode.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 02h-   | PREV        | Pointer to previous       | Set by the       |
    
    | 03h    |             | resource block.           | Realtime Control |
    
    |        |             |                           | Microcode.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 04h    | 09h         | Block descriptor.         | = 09h            |
    
    +--------+-------------+---------------------------+------------------+
    
    | 05h    | SCCNUM      | SCC port number.          | Dependent on the |
    
    |        |             |                           | co-processor     |
    
    |        |             |                           | adapter and the  |
    
    |        |             |                           | interface board  |
    
    |        |             |                           | installed.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 06h    | SCCTSK      | Owner task number.        |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 07h    | RESERVED    | Reserved.                 | Must be 0.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 08h-   | XMITOFF     | SCC transmit interrupt    |                  |
    
    | 09h    |             | vector.                   |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 0Ah-   | XMITSEG     | Segment to transmit       |                  |
    
    | 0Bh    |             | interrupt vector.         |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 0Ch-   | RECOFF      | Offset to receive         |                  |
    
    | 0Dh    |             | interrupt vector for      |                  |
    
    |        |             | SCC receive interrupt.    |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 0Eh-   | RECSEG      | Segment to receive        |                  |
    
    | 0Fh    |             | interrupt vector.         |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 10h-   | ERROFF      | Offset to error           |                  |
    
    | 11h    |             | interrupt vector.         |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 12h-   | ERRSEG      | Segment to error          |                  |
    
    | 13h    |             | interrupt vector.         |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 14h-   | EXTOFF      | Offset to external        |                  |
    
    | 15h    |             | interrupt vector.         |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 16h-   | EXTSEG      | Segment to external       |                  |
    
    | 17h    |             | interrupt vector.         |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 18h-   | SCCBAS      | SCC base register         | Set by the       |
    
    | 19h    |             | address.                  | Realtime Control |
    
    |        |             |                           | Microcode.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 1Ah-   | SCCRELINT   | SCC release interrupt     | Set by the       |
    
    | 1Bh    |             | address.                  | Realtime Control |
    
    |        |             |                           | Microcode.       |
    
    +--------+-------------+---------------------------+------------------+
    
    

    SCC Port Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      09h        Resource block descriptor
    
      SCCTSK     Owner task number
    
      SCCNUM     SCC port number
    
      xxxOFF     Requested Interrupt vector offset (dependent
    
                 on type of service)
    
      xxxSEG     Requested interrupt vector segment
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      SCCBAS     SCC base address
    
      SCCRELINT  SCC release interrupt address
    
    

    Allocation of SCC Ports

    Ownership of SCC Ports

    Deallocation of SCC Ports

    SVC 47h is used to return ownership of the particular SCC port to the control of the Realtime Control Microcode.

    Associated Interface Modules

    
    
    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    INT A2h         SCCRESET
    
    
    
     PROM Service    INT A4h         SCCREGS
    
    
    
     Diagnostic      AH = 09h,       CONFIGURE
    
     Test            INT = FEh       SCC CHANNEL
    
    
    
    

    CIO Ports (0Ah)

    The CIO port resource consists of one CIO port. This resource should be allocated only when the Communications port type resource is too restrictive. An example of this is where the CIO port definitions have been modified to support a custom interface board. This resource type is provided to allow dedicated software systems or communications subsystems access to the primitive hardware resource. Valid CIO ports are 0-3 on a Multiport Adapter, Model 2 or a Portmaster Adapter/A.

    CIO Port Resource Block

    The CIO port resource block (CIORB) is defined in the table that follows:

    Purpose:
    Used to allocate and return a CIO port

    Location:
    Task header segment in task storage

    Size:
    10h bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------------+
    
    
    
    | CIO Port Resource Block                                             |
    
    
    
    +--------+-------------+---------------------------+------------------+
    
    
    
    | Byte   | Field Name  | Description               | Comments         |
    
    
    
    +--------+-------------+---------------------------+------------------+
    
    | 00h-   | NEXT        | Pointer to next resource  | Set by the       |
    
    | 01h    |             | block.                    | Realtime Control |
    
    |        |             |                           | Microcode.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 02h-   | PREV        | Pointer to previous       | Set by the       |
    
    | 03h    |             | resource block.           | Realtime Control |
    
    |        |             |                           | Microcode.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 04h    | 0Ah         | Block descriptor.         | = 0Ah            |
    
    +--------+-------------+---------------------------+------------------+
    
    | 05h    | CIONUM      | CIO port number.          | Dependent on     |
    
    |        |             |                           | co-processor     |
    
    |        |             |                           | adapter          |
    
    |        |             |                           | (see note).      |
    
    +--------+-------------+---------------------------+------------------+
    
    | 06h    | CIOTSK      | Owner task number.        |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 07h    | RESERVED    | Reserved.                 | Must be 0.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 08h-   | CIOOFF      | CIO interrupt vector      | Offset           |
    
    | 09h    |             | offset.                   |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 0Ah-   | CIOSEG      | CIO interrupt vector      | Segment          |
    
    | 0Bh    |             | segment.                  |                  |
    
    +--------+-------------+---------------------------+------------------+
    
    | 0Ch-   | CIOBAS      | CIO base register         | Set by the       |
    
    | 0Dh    |             | address.                  | Realtime Control |
    
    |        |             |                           | Microcode.       |
    
    +--------+-------------+---------------------------+------------------+
    
    | 0Eh-   | CIORELINT   | CIO release interrupt     | Set by the       |
    
    | 0Fh    |             | address.                  | Realtime Control |
    
    |        |             |                           | Microcode.       |
    
    +--------+-------------+---------------------------+------------------+
    
    

    Note:

    See the "Entry Parameters" heading under the , for a discussion on CIO port numbering.

    CIO Port Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      0Ah        Resource block descriptor
    
      CIONUM     CIO port number
    
      CIOOFF     Requested interrupt vector offset (dependent
    
                 on type of service)
    
      CIOSEG     Requested interrupt vector segment
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      CIOBAS     CIO register address
    
      CIORELINT  CIO release interrupt address
    
    

    Allocation of CIO Ports

    Ownership of CIO Ports

    Deallocation of CIO Ports

    SVC 47h is used to return ownership of the particular CIO port to the control of the Realtime Control Microcode.

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    INT A6h         CIOREGS
    
    
    
     Diagnostic      AH = 08h,       CONFIGURE
    
     test            INT = FEh       CIO PORT
    
    
    
     Service         AH = 06h,       READ/WRITE
    
     Interrupt       INT = 74h       CIO BITS
    
    

    Communications Port (0Ch)

    The communications port incorporates a single communications port, a pair of DMA channels, and the CIO bits associated with the specified port into a single package. This is the preferred method of allocating a communications port since all the resources for the requested port interface type are acquired at the same time.

    Communications Port Resource Block

    The communications port resource block is defined in the table that follows:

    Purpose:
    Used to allocate and return a communications port

    Location:
    Task header segment in task storage

    Size:
    2Eh bytes per block

    Initialization:
    Initial values set by task
    
    +---------------------------------------------------------------------+
    
    
    
    | Communications Port Resource Block                                  |
    
    
    
    +--------+-------------+------------------------------+---------------+
    
    
    
    | Byte   | Field Name  | Description                  | Comments      |
    
    
    
    +--------+-------------+------------------------------+---------------+
    
    | 00h-01h| NEXT        | Pointer to next block in     |               |
    
    |        |             | list; set by Realtime        |               |
    
    |        |             | Control Microcode.           |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 02h-03h| PREV        | Pointer to previous block    |               |
    
    |        |             | in list; set by Realtime     |               |
    
    |        |             | Control Microcode.           |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 04h    | 0Ch         | Block descriptor.            | = 0Ch         |
    
    +--------+-------------+------------------------------+---------------+
    
    | 05h    | CPNUM       | Communications port number.  |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 06h    | TSKNUM      | Owner task number of this    |               |
    
    |        |             | block.                       |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 07h    | Reserved    | Reserved.                    | Must be 0.    |
    
    +--------+-------------+------------------------------+---------------+
    
    | 08h-0Eh| XMITVECT    | SCC transmit interrupt       |               |
    
    |        |             | vector.                      |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 0Ch-0Fh| RECVECT     | SCC receive interrupt        |               |
    
    |        |             | vector.                      |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 10h-13h| ERRVECT     | SCC error interrupt vector.  |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 14h-17h| EXTVECT     | SCC external interrupt       |               |
    
    |        |             | vector.                      |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 18h-19h| SCCBASE     | SCC base address; set by     |               |
    
    |        |             | Realtime Control Microcode.  |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 1Ah-1Bh| SCCRELINT   | SCC release interrupt        |               |
    
    |        |             | address; set by Realtime     |               |
    
    |        |             | Control Microcode.           |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 1Ch-1Dh| RXDMABAS    | Receive DMA base address;    |               |
    
    |        |             | set by Realtime Control      |               |
    
    |        |             | Microcode.                   |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 1Eh-1Fh| TXDMABAS    | Transmit DMA base address;   |               |
    
    |        |             | set by Realtime Control      |               |
    
    |        |             | Microcode.                   |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 20h-21h| RXDRELINT   | Receive DMA release          |               |
    
    |        |             | interrupt address; set by    |               |
    
    |        |             | Realtime Control Microcode.  |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 22h-23h| TXDRELINT   | Transmit DMA release         |               |
    
    |        |             | interrupt address; set by    |               |
    
    |        |             | Realtime Control Microcode.  |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 24h-27h| RXDMAVEC    | Receive DMA vector.          |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 28h-2Bh| TXDMAVEC    | Transmit DMA vector.         |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 2Ch    | PORTTYPE    | Port interface type          | See port types|
    
    |        |             | requested by user,           | below.        |
    
    |        |             | returned by Realtime         |               |
    
    |        |             | Control Microcode.           |               |
    
    |        |             | See figure and text.         |               |
    
    +--------+-------------+------------------------------+---------------+
    
    | 2Dh    | SCCTYPE     | Communications chip type     | See SCC types |
    
    |        |             | requested by user,           | below.        |
    
    |        |             | returned by Realtime         |               |
    
    |        |             | Control Microcode.           |               |
    
    +--------+-------------+------------------------------+---------------+
    
    
    
     PORTTYPE =   Port interface type
    
    
    
                  00h = RS-232-C
    
                  01h = RS-422-A
    
    
    
                  02h-FDh = reserved
    
                  FEh = Unknown
    
                  FFh = reserved, see text that follows
    
    
    
     SCCTYPE =    Communications chip type
    
                  00h = Zilog SCC
    
                  01h = Signetics DUSCC
    
    
    
                  02h-FDh = reserved
    
                  FEh = Unknown
    
    
    
                  FFh = reserved, see text on the next page
    
    
    
    

    Communications Port Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      0Ch        Resource block descriptor
    
      TSKNUM     Owner task number
    
      CPNUM      Communications port number
    
      xxxOFF     Requested Interrupt vector offset (dependent
    
                 on type of service)
    
      xxxSEG     Requested interrupt vector segment
    
      PORTTYPE   Interface type (optional)
    
      SCCTYPE    Communications chip type (optional)
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
      SCCBAS     SCC base address
    
      SCCRELINT  SCC release interrupt address
    
      TXDRELINT  Transmit DMA channel release interrupt address
    
      RXDRELINT  Receive DMA channel release interrupt address
    
      PORTTYPE   Interface type
    
      SCCTYPE    Communications chip type
    
    

    Allocation of Communications Ports

    Ownership of Communications Ports

    Deallocation of Communications Ports

    SVC 47h is used to return ownership of the particular communications port to the control of the Realtime Control Microcode.

    Associated Interface Modules

    
    
    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    INT A2h         SCCRESET
    
    
    
     PROM Service    INT A4h         SCCREGS
    
    
    
     PROM Service    INT B2h         DMAADDR
    
    
    
     PROM Service    AH = 00h        SEG2PHYT
    
                     INT CEh
    
    
    
     PROM Service    AH = 02         PDMAREGS
    
                     INT CEh
    
    
    
     Diagnostic      AH = 09h        CONFIGURE
    
     Test            INT  FEh        SCC CHANNEL
    
    
    
     Service         AH = 06h        MAP/UNMAP EMM
    
     Interrupt       INT  72h        HANDLE PAGES
    
    
    
     Service         AH = 07h        MAP/UNMAP PHYSICAL
    
     Interrupt       INT  72h        MEMORY
    
    
    
     Service         AH = 08h        EMM HANDLE TO
    
     Interrupt       INT  72h        PHYSICAL ADDRESS
    
    
    
     Service         AH = 0Ah        PUSH PAGE MAP
    
     Interrupt       INT  72h
    
    
    
     Service         AH = 0Bh        POP PAGE MAP
    
     Interrupt       INT  72h
    
    
    
     Service         AH = 00h        HALF RATE SELECT
    
     Interrupt       INT  74h        CONTROL
    
    
    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     Service         AH = 01h        TRANSMIT CONTROL
    
     Interrupt       INT  74h
    
    
    
     Service         AH = 02h        RTS/DTR CONTROL
    
     Interrupt       INT  74h
    
    
    
     Service         AH = 03h        QUERY EXTERNAL/STATUS
    
     Interrupt       INT  74h        CONTROL
    
    
    
     Service         AH = 04h        EXTERNAL STATUS
    
     Interrupt       INT  74h        INTERRUPT CONTROL
    
    
    
     Service         AH = 05h        CLEAR EXTERNAL/STATUS
    
     Interrupt       INT  74h        INTERRUPT
    
    

    Expanded Memory Pages Resource Block (0Dh)

    Expanded memory allows for data storage in memory beyond the 1MB addressing capability of the 80186. It is supported on Portmaster Adapter/A adapters only. The functions of the expanded memory manager (EMM) for the Realtime Control Microcode are based upon the Lotus**/Intel**/Microsoft** Expanded Memory Specification Version 4.0 (LIM).

    Expanded memory can be allocated in contiguous or non-contiguous 16-kilobyte pages. A user task specifies the number of pages required and whether the pages must be contiguous.

    Because an 80186 logical address (segment:offset) can only address up to 1MB of memory, an expanded memory page is addressed using an EMM handle address. An EMM handle address is composed of an EMM handle, a logical page number, and an offset. The EMM handle is returned by Realtime Control Microcode upon allocation; the logical page numbers start at 0 and increase to the number of allocated pages minus 1; and the offset ranges from 0000h to 3FFFh.

    Expanded Memory Resource Block Definition

    The expanded memory resource block (EMRB) is defined in the table that follows.

    Purpose:
    To allocate and return expanded memory

    Location:
    Task header in task storage

    Size:
    0Eh bytes per block

    .Initialization:
    Initial values set by task.
    
    +---------------------------------------------------------------------+
    
    
    
    | Expanded Memory Resource Block                                      |
    
    
    
    +--------+------------+-----------------------------------+-----------+
    
    
    
    | Byte   | Field Name | Description                       | Comments  |
    
    
    
    +--------+------------+-----------------------------------+-----------+
    
    | 00h-   | NEXT       | Pointer to next block in list;    |           |
    
    | 01h    |            | set by Realtime Control Microcode.|           |
    
    +--------+------------+-----------------------------------+-----------+
    
    | 02h-   | PREV       | Pointer to previous block in list;|           |
    
    | 03h    |            | set by Realtime Control Microcode.|           |
    
    +--------+------------+-----------------------------------+-----------+
    
    | 04h    | 0Dh        | Block descriptor.                 | = 0Dh     |
    
    +--------+------------+-----------------------------------+-----------+
    
    | 05h    | EMCONT     | Contiguous pages flag.            |           |
    
    |        |            | 00h = pages can be scattered.     |           |
    
    |        |            | 01h = pages must be contiguous.   |           |
    
    +--------+------------+-----------------------------------+-----------+
    
    | 06h    | EMMTSK     | Owner task number of this block.  |           |
    
    +--------+------------+-----------------------------------+-----------+
    
    | 07h    | Reserved   | Reserved.                         | Must be 0.|
    
    +--------+------------+-----------------------------------+-----------+
    
    | 08h-   | EMMPAGES   | Number of 16KB expanded memory    |           |
    
    | 09h    |            | pages requested.                  |           |
    
    +--------+------------+-----------------------------------+-----------+
    
    | 0Ah-   | EMMHANDLE  | EMM handle for allocated pages;   |           |
    
    | 0Eh    |            | set by Realtime Control Microcode.|           |
    
    +--------+------------+-----------------------------------+-----------+
    
    | 0Ch-   | Reserved   | Reserved.                         | Must be 0.|
    
    | 0Dh    |            |                                   |           |
    
    +--------+------------+-----------------------------------+-----------+
    
    

    Before the allocation request, the task must complete the following fields in the resource block:

    
      0Dh         Resource block descriptor
    
      EMCONT      Contiguous page flag
    
      EMMTSK      Owner task number
    
      EMMPAGES    Number of pages requested
    
    

    The Realtime Control Microcode completes the following fields in the resource block:

    
      NEXT        Pointer to next block in list
    
      PREV        Pointer to previous block in list
    
      EMMHANDLE   EMM handle for allocated pages
    
    

    Allocation of Expanded Memory

    SVC 46h is used to allocate temporary ownership of the expanded memory pages.

    The following services are used to map the different address formats into 80186 addressable logical address:

    Deallocation of Expanded Memory

    SVC 47h is used to return expanded memory pages.

    Associated Interface Modules

    
    
    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    AH = 00h        SEG2PHYT
    
                     INT CEh
    
    
    
     PROM Service    AH = 01h        PHY2PAG
    
                     INT CEh
    
    
    
     Service         AH = 04h        GET PAGE FRAME
    
     Interrupt       INT  72h        SEGMENT ADDRESS
    
    
    
     Service         AH = 05h        GET UNALLOCATED
    
     Interrupt       INT  72h        PAGE COUNT
    
    
    
     Service         AH = 06h        MAP/UNMAP EMM
    
     Interrupt       INT  72h        HANDLE PAGES
    
    
    
     Service         AH = 07h        MAP/UNMAP PHYSICAL
    
     Interrupt       INT  72h        MEMORY
    
    
    
     Service         AH = 08h        EMM HANDLE TO
    
     Interrupt       INT  72h        PHYSICAL ADDRESS
    
    
    
     Service         AH = 09h        EMM HANDLE TO PAGE
    
     Interrupt       INT  72h        OFFSET ADDRESS
    
    
    
     Service         AH = 0Ah        PUSH PAGE MAP
    
     Interrupt       INT  72h
    
    
    
     Service         AH = 0Bh        POP PAGE MAP
    
     Interrupt       INT  72h
    
    

    Extended Service Hooks Resource Block (0Eh)

    Extended service hooks are provided for users that need to extend the capabilities of Realtime Control Microcode. This resource block may be used to allocate one or more hooks into any Realtime Control Microcode command, supervisor call, service interrupt, or the dispatch cycle. Any number of tasks can request the same hook.

    Each of the extended service hooks falls into one of three access categories based on the action the extension is to perform. The first category is pre-process. It is used when a user needs to gain control and do some processing prior to Realtime Control Microcode actually performing the originally requested service. When multiple pre-process resource blocks exist for the same hook, Realtime Control Microcode links them such that the last pre-process requester receives control first.

    The second category is replace. It is used when a user needs to gain control and do the service processing in lieu of Realtime Control Microcode. When there are multiple replace resource blocks for the same hook, Realtime Control Microcode links them such that the last replace requestor gets control last.

    The third category is monitor, which is similar to pre-process. The difference is that when multiple monitor resource blocks exist, Realtime Control Microcode links them such that the last monitor requestor receives control last.

    When a mix of resource block categories exists on a single hook, Realtime Control Microcode links them such that all pre-process requestors get control first, followed by monitor, and last, replace.

    Extended Service Hooks Resource Block Definition

    The extended service hooks resource block (EMRB) is defined in the table that follows.

    Purpose:
    To allocate and return extended service hooks

    Location:
    Task header in task storage

    Size:
    20h bytes per block

    Initialization:
    Initial values set by task.
    
    +----------------------------------------------------------------------+
    
    
    
    | Extended Service Hooks Resource Block                                |
    
    
    
    +--------+------------+-----------------------------------+------------+
    
    
    
    | Byte   | Field Name | Description                       | Comments   |
    
    
    
    +--------+------------+-----------------------------------+------------+
    
    | 00h-   | NEXT       | Pointer to next block in list;    |            |
    
    | 01h    |            | set by Realtime Control Microcode.|            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 02h-   | PREV       | Pointer to previous block in list;|            |
    
    | 03h    |            | set by Realtime Control Microcode.|            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 04h    |  0Eh       | Block descriptor.                 | = 0Eh      |
    
    +--------+------------+-----------------------------------+------------+
    
    | 05h    | HTYPE      | Type of hook; set by requestor.   | See        |
    
    |        |            |                                   | following  |
    
    |        |            |                                   | table.     |
    
    +--------+------------+-----------------------------------+------------+
    
    | 06h    | TSKNUM     | Owner task number of this block;  |            |
    
    |        |            | set by requestor.                 |            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 07h    | Reserved   | Reserved.                         | Must be 0. |
    
    +--------+------------+-----------------------------------+------------+
    
    | 08h    | HNUM       | Hook number requested;            | See        |
    
    |        |            | set by requestor.                 | following  |
    
    |        |            |                                   | tables.    |
    
    +--------+------------+-----------------------------------+------------+
    
    | 09h    | HACCAT     | Access category of hook;          | See note 1.|
    
    |        |            | set by requestor.                 |            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 0Ah-   | Reserved   | Reserved.                         | Must be 0. |
    
    | 0Bh    |            |                                   |            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 0Ch-   | USEROFF    | Offset of user routine;           |            |
    
    | 0Dh    |            | set by requestor.                 |            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 0Eh-   | USERSEF    | Segment of user routine;          |            |
    
    | 0Fh    |            | set by requestor.                 |            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 10h-   | NORMOFF    | Offset of normal exit;            | See note 2.|
    
    | 11h    |            | set by Realtime Control Microcode.|            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 12h-   | NORMSEG    | Segment of normal exit;           | See note 2.|
    
    | 13h    |            | set by Realtime Control Microcode.|            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 14h-   | QUICKOFF   | Offset of quick exit;             | See note 3.|
    
    | 15h    |            | set by Realtime Control Microcode.|            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 16h-   | QUICKSEG   | Segment of quick exit;            | See note 3.|
    
    | 17h    |            | set by Realtime Control Microcode.|            |
    
    +--------+------------+-----------------------------------+------------+
    
    | 18h-   | Reserved   | Reserved for Realtime Control     |            |
    
    | 1Fh    |            | Microcode use.                    |            |
    
    +--------+------------+-----------------------------------+------------+
    
    

    Notes:

    1. HACCAT = Hook access type:
      00h = Monitor access
      01h = Pre-Process access
      02h = Replace access
    2. NORMOFF/NORMSEG-&dashnormal exit. All tasks having a Monitor or Pre-Process access should use the normal exit to return control to the Realtime Control Microcode. Tasks having Replace access should use this exit if they do not want to process the hook.
    3. QUICKOFF/QUICKSEG-&dashquick exit. Tasks having Replace access to a hook should use this exit to return control to the Realtime Control Microcode after processing the hook.

    HTYPE (hook type) and HNUM (hook number) values are shown in the following tables. Note that the value of HNUM depends on the HTYPE.

    
    +---------------------------------------------------------------------+
    
    
    
    | HTYPE Values                                                        |
    
    
    
    +------------+--------------------------------------------------------+
    
    
    
    | HTYPE      | Type of Hook                                           |
    
    
    
    +------------+--------------------------------------------------------+
    
    | 00h        | CMD from system unit                                   |
    
    +------------+--------------------------------------------------------+
    
    | 01h        | SVC (except for allocate and return SVCs)              |
    
    +------------+--------------------------------------------------------+
    
    | 02h        | Alloc SVC                                              |
    
    +------------+--------------------------------------------------------+
    
    | 03h        | Return SVC                                             |
    
    +------------+--------------------------------------------------------+
    
    | 04h        | SVI (except ESIR)                                      |
    
    +------------+--------------------------------------------------------+
    
    | 05h        | ESIR (XSVI)                                            |
    
    +------------+--------------------------------------------------------+
    
    | 06h        | Other routines                                         |
    
    +------------+--------------------------------------------------------+
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | HNUM Values for Command Hooks                                       |
    
    
    
    +----------+---------------------------+------------------------------+
    
    
    
    | HNUM     | Command                   | Hook Category                |
    
    
    
    +----------+---------------------------+------------------------------+
    
    | 00h      | INITIALIZE CMD            | Monitor                      |
    
    +----------+---------------------------+------------------------------+
    
    | 01h      | REQUEST TASK LOAD         | Monitor/pre-process          |
    
    +----------+---------------------------+------------------------------+
    
    | 02h      | FREE BUFFER               | Monitor                      |
    
    +----------+---------------------------+------------------------------+
    
    | 03h      | REQUEST TASK LOAD         | Monitor/pre-process          |
    
    |          | WITH BOUNDARY             |                              |
    
    +----------+---------------------------+------------------------------+
    
    | 04h      | QUERY FREE STORAGE        | Monitor                      |
    
    +----------+---------------------------+------------------------------+
    
    | 05h      | START TASK                | Monitor/pre-process          |
    
    +----------+---------------------------+------------------------------+
    
    | 06h      | STOP TASK                 | Monitor/pre-process          |
    
    +----------+---------------------------+------------------------------+
    
    | 07h      | UNLOAD TASK               | Monitor/pre-process          |
    
    +----------+---------------------------+------------------------------+
    
    | 08h      | SET WATCHDOG TIMER        | Monitor                      |
    
    |          | DURATION                  |                              |
    
    +----------+---------------------------+------------------------------+
    
    | 09h      | ENABLE WATCHDOG TIMER     | Monitor                      |
    
    +----------+---------------------------+------------------------------+
    
    | 0Ah      | DISABLE WATCHDOG TIMER    | Monitor                      |
    
    +----------+---------------------------+------------------------------+
    
    | 0Bh      | READ WATCHDOG TIMER       | Monitor                      |
    
    +----------+---------------------------+------------------------------+
    
    | 0Ch      | REQUEST TASK LOAD LOW     | Monitor/pre-process          |
    
    +----------+---------------------------+------------------------------+
    
    | 0Dh      | SET TIME                  | Monitor/pre-process          |
    
    +----------+---------------------------+------------------------------+
    
    | 0Eh      | GET TIME                  | Monitor/pre-process          |
    
    +----------+---------------------------+------------------------------+
    
    | 1Fh      | ILLEGAL CMD               | Monitor/pre-process/replace  |
    
    +----------+---------------------------+------------------------------+
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | HNUM Values for SVC Hooks                                           |
    
    
    
    +------------+-----------------------+--------------------------------+
    
    
    
    | HNUM       | SVC                   | Hook Category                  |
    
    
    
    +------------+-----------------------+--------------------------------+
    
    | 37h        | INTPC                 | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 38h        | UNLOAD                | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 39h        | BUILD                 | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 3Ah        | START                 | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 3Bh        | STOP                  | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 3Ch        | WAIT                  | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 3Dh        | SUSPEND               | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 3Eh        | RESUME                | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 3Fh        | POST                  | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 40h        | ASAP                  | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 41h        | STAYRES               | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 42h        | READVEC               | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 43h        | TIMERP                | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 44h        | TIMER                 | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 45h        | CANCEL                | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 46h        | Reserved              |                                |
    
    +------------+-----------------------+--------------------------------+
    
    | 47h        | Reserved              |                                |
    
    +------------+-----------------------+--------------------------------+
    
    | 48h        | INITCOMP              | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 49h        | QFREST                | Monitor/pre-process            |
    
    +------------+-----------------------+--------------------------------+
    
    | 7Fh        | Illegal SVC           | Monitor/pre-process/replace    |
    
    +------------+-----------------------+--------------------------------+
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | HNUM Values for Resource Allocate                                   |
    
    
    
    +----------+----------------------------+-----------------------------+
    
    
    
    | HNUM     | Resource Allocate          | Hook Category               |
    
    
    
    +----------+----------------------------+-----------------------------+
    
    | 01h      | User-Requestable interrupt | Monitor/pre-process         |
    
    |          | Vector                     |                             |
    
    +----------+----------------------------+-----------------------------+
    
    | 02h      | RAM                        | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 03h      | Reserved                   |                             |
    
    +----------+----------------------------+-----------------------------+
    
    | 04h      | DMA Channel                | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 05h      | User Queue                 | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 06h      | H/W Timer                  | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 07h      | S/W Timer                  | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 08h      | Reserved                   |                             |
    
    +----------+----------------------------+-----------------------------+
    
    | 09h      | SCC Port                   | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Ah      | CIO Port                   | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Bh      | Reserved                   |                             |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Ch      | Comm Port                  | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Dh      | EMM Pages                  | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Eh      | Extended Service Hooks     | Monitor                     |
    
    +----------+----------------------------+-----------------------------+
    
    | 1Fh      | Illegal Allocate           | Monitor/pre-process/replace |
    
    +----------+----------------------------+-----------------------------+
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | HNUM Value for Resource Return                                      |
    
    
    
    +----------+----------------------------+-----------------------------+
    
    
    
    | HNUM     | Resource Return            | Hook Category               |
    
    
    
    +----------+----------------------------+-----------------------------+
    
    | 01h      | User-Requestable interrupt | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 02h      | RAM                        | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 03h      | Reserved                   |                             |
    
    +----------+----------------------------+-----------------------------+
    
    | 04h      | DMA Channel                | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 05h      | User Queue                 | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 06h      | H/W Timer                  | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 07h      | S/W Timer                  | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 08h      | Reserved                   |                             |
    
    +----------+----------------------------+-----------------------------+
    
    | 09h      | SCC Port                   | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Ah      | CIO Port                   | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Bh      | Reserved                   |                             |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Ch      | Comm Port                  | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Dh      | EMM Pages                  | Monitor/pre-process         |
    
    +----------+----------------------------+-----------------------------+
    
    | 0Eh      | Extended Service Hooks     | Monitor                     |
    
    | 0Eh      |                            |                             |
    
    +----------+----------------------------+-----------------------------+
    
    | 1Fh      | Illegal Return             | Monitor/pre-process/replace |
    
    +----------+----------------------------+-----------------------------+
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | HNUM Values for SVIs                                                |
    
    
    
    +----------+------------------+---------------------------------------+
    
    
    
    | HNUM     | SVI              | Hook Category                         |
    
    
    
    +----------+------------------+---------------------------------------+
    
    | 00h      | SEG2PAGE         | Monitor/pre-process                   |
    
    +----------+------------------+---------------------------------------+
    
    | 01h      | PAGE2SEG         | Monitor/pre-process                   |
    
    +----------+------------------+---------------------------------------+
    
    | 02h      | POSTI            | Monitor/pre-process                   |
    
    +----------+------------------+---------------------------------------+
    
    | 03h      | RESUMEI          | Monitor/pre-process                   |
    
    +----------+------------------+---------------------------------------+
    
    | 04h      | CANCELI          | Monitor/pre-process                   |
    
    +----------+------------------+---------------------------------------+
    
    | 05h      | RECQUEUE         | Monitor/pre-process/replace           |
    
    +----------+------------------+---------------------------------------+
    
    | 06h      | ADDQUEUE         | Monitor/pre-process/replace           |
    
    +----------+------------------+---------------------------------------+
    
    | 07h      | REMQUEUE         | Monitor/pre-process/replace           |
    
    +----------+------------------+---------------------------------------+
    
    | 08h      | TRANSSEG         | Monitor/pre-process                   |
    
    +----------+------------------+---------------------------------------+
    
    | 09h      | Reserved         |                                       |
    
    +----------+------------------+---------------------------------------+
    
    | 0Ah      | LCLS             | Monitor/pre-process                   |
    
    +----------+------------------+---------------------------------------+
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | HNUM Values for Extended SVIs                                       |
    
    
    
    +----------+--------------------------+-------------------------------+
    
    
    
    | HNUM     | Extended SVI             | Hook Category                 |
    
    
    
    +----------+--------------------------+-------------------------------+
    
    | 00h      | DISABLE PREEMPTION       | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 01h      | ENABLE PREEMPTION        | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 02h      | GET TASK IN EXEC         | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 03h      | PEER REQUEST             | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 04h      | GET PAGE FRAME SEGMENT   | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 05h      | GET UNALLOCATED PAGE     | Monitor/pre-process           |
    
    |          | COUNT                    |                               |
    
    +----------+--------------------------+-------------------------------+
    
    | 06h      | MAP/UNMAP EMM HANDLE     | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 07h      | MAP/UNMAP PHYSICAL MEM   | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 08h      | EMM HANDLE TO PHYSICAL   | Monitor/pre-process           |
    
    |          | ADDRESS                  |                               |
    
    +----------+--------------------------+-------------------------------+
    
    | 09h      | EMM HANDLE TO PAGE       | Monitor/pre-process           |
    
    |          | OFFSET ADDRESS           |                               |
    
    +----------+--------------------------+-------------------------------+
    
    | 0Ah      | PUSH PAGE MAP            | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 0Bh      | POP PAGE MAP             | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 0Ch      | PHYSICAL ADDQUEUE        | Monitor/pre-process/replace   |
    
    +----------+--------------------------+-------------------------------+
    
    | 0Dh      | GET/SET TIME             | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 0Eh      | GET INTERRUPT STATUS     | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 0Fh      | GET RESOURCE COUNT       | Monitor/pre-process           |
    
    +----------+--------------------------+-------------------------------+
    
    | 10h      | GET CALLABLE ROUTINE     | Monitor/pre-process           |
    
    |          | ADDRESS                  |                               |
    
    +----------+--------------------------+-------------------------------+
    
    | 11h      | GET NEXT AVAILABLE       | Monitor/pre-process           |
    
    |          | RESOURCE                 |                               |
    
    +----------+--------------------------+-------------------------------+
    
    | 7Fh      | Illegal ESIR             | Monitor/pre-process/replace   |
    
    +----------+--------------------------+-------------------------------+
    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | HNUM Miscellaneous Values                                           |
    
    
    
    +----------+--------------------------------+-------------------------+
    
    
    
    | HNUM     | Miscellaneous                  | Hook Category           |
    
    
    
    +----------+--------------------------------+-------------------------+
    
    | 00h      | Interrupt from system unit     | Monitor/pre-process     |
    
    +----------+--------------------------------+-------------------------+
    
    | 01h      | Dispatch                       | Monitor/pre-process     |
    
    +----------+--------------------------------+-------------------------+
    
    

    For all hooks except Dispatch, user hook routines receive control with all registers of the calling task preserved except for BX, DS, ES, SI. These registers are passed on the stack along with other pertinent information. The stack layout is shown in the following chart:

    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | Extended Service Hooks Stack Frame Layout - Type 1                  |
    
    
    
    +---------+------------+-----------------------------------+----------+
    
    
    
    | Stack   | Field Name |  Description                      | Comments |
    
    | Location|            |                                   |          |
    
    
    
    +---------+------------+-----------------------------------+----------+
    
    | SP      | ES         | Copy of calling task's ES register|          |
    
    +---------+------------+-----------------------------------+----------+
    
    | SP+02h  | DS         | Copy of calling task's DS register|          |
    
    +---------+------------+-----------------------------------+----------+
    
    | SP+04h  | SI         | Copy of calling task's SI register|          |
    
    +---------+------------+-----------------------------------+----------+
    
    | SP+06h  | BX         | Copy of calling task's BX register|          |
    
    +---------+------------+-----------------------------------+----------+
    
    | SP+08h  | HWINTCNT   | Depth of hardware interrupts      |          |
    
    |         |            | A 0 = no hardware interrupts      |          |
    
    +---------+------------+-----------------------------------+----------+
    
    | SP+0Ah  | PREREQ     | Preemption request                |          |
    
    |         |            | Set to 00h on entry.              |          |
    
    |         |            | Set to 01h by hook to request     |          |
    
    |         |            | preemption by Realtime Control    |          |
    
    |         |            | Microcode.                        |          |
    
    +---------+------------+-----------------------------------+----------+
    
    | SP+0Ch  | TCB@       | Far pointer to caller's TCB       |          |
    
    +---------+------------+-----------------------------------+----------+
    
    

    The DISPATCH hook receives its parameters through the stack frame shown in the following chart.

    
    +---------------------------------------------------------------------+
    
    
    
    | Extended Service Hooks Stack Frame Layout - Type 2                  |
    
    
    
    +---------+------------+-----------------------------------+----------+
    
    
    
    | Stack   | Field Name | Description                       | Comments |
    
    | Location|            |                                   |          |
    
    
    
    +---------+------------+-----------------------------------+----------+
    
    | SP+04h  | TCBNXT@    | Far pointer to next TCB in the    |          |
    
    |         |            | dispatch queue.                   |          |
    
    +---------+------------+-----------------------------------+----------+
    
    | SP      | TCBPREV    | Far pointer to previous TCB in    |          |
    
    |         |            | the dispatch queue.               |          |
    
    +---------+------------+-----------------------------------+----------+
    
    

    Extended Service Hooks Resource Block Definition

    Before the allocation request, the task must complete the following fields in the resource block:

    
      0Eh        Resource block descriptor
    
      HTYPE      Type of hook
    
      TSKNUM     Owner task number
    
      HNUM       Hook number
    
      HACCAT     Hook access category
    
      xxxOFF     Requested vector offset
    
      xxxSEG     Requested vector segment
    
    
    
    

    The Realtime Control Microcode completes the following fields:

    
      NEXT       Pointer to next block in list
    
      PREV       Pointer to previous block in list
    
    

    Allocation of Extended Service Hooks

    SVC 46h is used to allocate ownership of an extended service hook.

    Deallocation of Extended Service Hook

    SVC 47h is used to return an extended service hook.

    Associated Interface Modules

    
    
    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     Service         AH = 0Eh        GET INTERRUPT
    
     Interrupt       INT  72h        COUNT
    
    
    
     Service         AH = 0Fh        GET RESOURCE
    
     Interrupt       INT  72h        COUNT
    
    
    
     Service         AH = 10h        GET CALLABLE
    
     Interrupt       INT  72h        ADDRESSES
    
    
    
     Service         AH = 10h        GET NEXT AVAILABLE
    
     Interrupt       INT  72h        RESOURCE
    
    

    First-Level Interrupt Handling

    The Realtime Control Microcode receives all interrupts, both hardware and software, and is responsible for processing them.

    The Realtime Control Microcode initializes interrupt vectors for each I/O interrupt to point to the Realtime Control Microcode first-level interrupt handler. When an application task requests a resource, the resource block contains the addresses of the task routines to handle interrupts for that particular resource. The Realtime Control Microcode has taken the task's interrupt handler addresses from the resource block and stored them in a separate internal table. When an I/O interrupt occurs, the Realtime Control Microcode gets control and performs a FAR CALL to the task's interrupt handler using the Realtime Control Microcode's first-level interrupt handler.

    Hardware Interrupt Processing

    Consider the following characteristics of the Realtime Control Microcode first-level hardware interrupt processing when writing your application task I/O interrupt handlers:

    Software Timer Interrupt Handling

    When a timer times out, a FAR CALL is made to the vector supplied by the user. The routine at that vector must execute a FAR RETURN when the routine finishes.

    Hardware Timer Interrupt Handling

    Under previous versions of the Realtime Control Microcode, no information was passed to a hardware timer interrupt handler. If a hardware timer error interrupt occurred, it was not handled by the Realtime Control Microcode and it was not passed on to the task. Hardware timer errors occur when a timer "pops" a second time before its first interrupt is serviced. This is a rare occurrence, because the interval of the periodic hardware timer must be very short for this to happen. To correct this situation, the Realtime Control Microcode passes a hardware timer error interrupt to the task's hardware timer interrupt handler. To enable the interrupt handler to distinguish between a normal timer interrupt and an error interrupt, a value is passed to the handler in register AX. Upon entry, a 0 in AX indicates a normal timer interrupt; a 1 in AX indicates a timer error interrupt.

    Command Interrupt Handling

    When the Realtime Control Microcode receives a task interrupt from the system unit, it sets the task busy and the output buffer busy in "primary status," and executes a CALL FAR to the subroutine pointed to by CVECT (command handler in the task header). The subroutine should POST the task with the new command post, and turn off the output buffer busy and the busy bit in the primary status byte for the task. The subroutine must also turn off the task's error bit in primary status. When the subroutine is finished, it must execute a RET FAR instruction to return to the Realtime Control Microcode.

    Software Interrupt Handling

    Consider the following characteristics of the Realtime Control Microcode first-level interrupt processing when handling software interrupts:

    Associated Interface Modules

    None.


    System Unit Interrupts

    Any co-processor adapter application task may interrupt the system unit. The co-processor adapter operates in the shared interrupt mode so multiple co-processor adapters may be assigned to the same interrupt level.

    Two services are provided so that tasks can interrupt the system unit: the Intpc SVC and the INTPCL PROM service.

    The Intpc SVC provides the user with a higher-level routine to interrupt the system unit. The Intpc SVC provides options to retry, request a restart of the system unit, "wait" the requesting task at the completion of the interrupt, and reset the busy and output buffer busy primary status bits.

    The INTPCL PROM service provides the task with a low-level routine to interrupt the system unit with no retry logic imbedded within the routine.

    The task should use the available interface routines to interrupt the system unit.

    To interrupt the system unit without using the provided services, the application task must execute the following:

    1. Check until the Interrupt ID byte (INTID) in the interface block contains FFh. A value of FFh indicates that the system unit is waiting to process the next interrupt.

    2. If FFh is the value found, proceed to step 3. If a value other than FFh is found, continue checking until FFh is found.

    3. Write the requesting task's task number in the Interrupt ID byte (INTID) in the interface block.

    4. Write the requesting task's task number in the I/O port 12h Task Register. This causes an interrupt to the system unit.

    5. The system unit's acceptance of the interrupt is indicated by the system unit writing FFh to the INTID in the interface block.

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    INT A0h         INTPCL
    
    
    
     SVC             INT 56h,        INTPC
    
                     AH=37h
    
    

    Peer Services

    The Realtime Control Microcode peer services provide a means for tasks to pass information among Portmaster Adapter/A adapters and the system unit. Using peer services, tasks can communicate with local tasks on the same Portmaster Adapter/A, remote tasks on a peer Portmaster Adapter/A, or applications in the system unit. For compatibility, the BCB command passing mechanism is preserved, but the peer services provide a more robust means of passing commands and data.

    Note:

    Realtime Control Microcode Version 2.01 allows a user to disable peer services. For additional information, see "Disabling Peer Services".

    Peer services provides two classes of message support. The first class does not acknowledge delivery of a message to its target, and, therefore, does not provide delivery notification. A requestor should use this class of service when guaranteed delivery is unimportant or an application task-level response provides delivery notification.

    The second class service provides delivery notification. The Realtime Control Microcode on the target processor positively acknowledges target task message delivery or negatively acknowledges lack of delivery. Lack of delivery can occur because the target task was unloaded, had insufficient buffer space to handle the incoming message, and so on. Additionally, the Realtime Control Microcode on the source processor watchdogs messages sent to the target processors in case of target processor failure or terminal error.

    The peer request SVI, PEER REQUEST, discussed in Volume II, is used to pass the messages between tasks/processors. Information concerning the peer request is passed in a peer request block, which is described in the following chart. Note that the Realtime Control Microcode supports a set of commands via peer requests, shown under "Realtime Control Microcode Peer Request Block Commands and Responses". The commands and data passed among application tasks are defined by the user.

    Realtime Control Microcode Peer Request Block

    The following chart shows the layout of the peer request block. The section that follows describes the fields within the request block.

    
    
    
                   +-----------------------------------------+
    
      Offset       | Field name                              |
    
                   +-----------------------------------------+
    
      00h-03h      | Queue chain                             |
    
                   +-----------------------------------------+
    
      04h          | Command/Response                        |
    
                   +-----------------------------------------+
    
      05h          | Completion code                         |
    
                   +-----------------------------------------+
    
      06h          | Peer request options                    |
    
                   +-----------------------------------------+
    
      07h          | Command options                         |
    
                   +-----------------------------------------+
    
      08h          | Target processor ID                     |
    
                   +-----------------------------------------+
    
      09h          | Source processor ID                     |
    
                   +-----------------------------------------+
    
      0Ah-0Bh      | Target task ID                          |
    
                   +-----------------------------------------+
    
      0Ch-0Dh      | Source task ID                          |
    
                   +-----------------------------------------+
    
      0Eh-0Fh      | Request block ID                        |
    
                   +-----------------------------------------+
    
      10h-11h      | Data byte count                         |
    
                   +-----------------------------------------+
    
      12h-13h      | Reserved                                |
    
                   +-----------------------------------------+
    
      14h-15h      | Data value 1 or immediate data          |
    
                   +-----------------------------------------+
    
      16h-17h      | Data address 1 or immediate data        |
    
                   +-----------------------------------------+
    
      1Ah-1Dh      | Data address 2 or immediate data        |
    
                   +-----------------------------------------+
    
      1Eh-21h      | Data address 3 or immediate data        |
    
                   +-----------------------------------------+
    
      22h-29h      | Reserved work area                      |
    
                   +-----------------------------------------+
    
    

    The following section describes the fields within the request block:

    Realtime Control Microcode Peer Request Block Commands and Responses

    Peer Request Commands

    The Realtime Control Microcode supports the following peer request commands.

    Move Data Command

    This command is issued to the Realtime Control Microcode to move data from one processor's memory to another processor's memory. A move data command can be issued to the Realtime Control Microcode on another processor.

    For Realtime Control Microcode 2.0, either the source buffer or the destination buffer (but not both) must be on the same processor as the Realtime Control Microcode that is issuing the command.

    For Realtime Control Microcode Version 2.01, the source buffer and/or the destination buffer must be on the same processor as the Realtime Control Microcode that is issuing the command. If both the source and destination buffers are on the same processor, the move data command is implemented by a memory move. If the source and destination buffers overlap, the integrity of the data is not guaranteed.

    
     ENTRY:
    
       Command                 02h
    
       Peer Request Options    0000 0maw
    
                               m = multiple block request.  When set, this is
    
                               the first block of a multiple block request.
    
                               a = acknowledge requested.  When set, provides
    
                               command handler notification when the command
    
                               is delivered to the target processor/task.  For
    
                               best performance, this bit should be 0 when
    
                               the target processor is the same as the source
    
                               processor.
    
                               w = wait requested.  When set, source task
    
                               is suspended until its peer request block
    
                               can be reused.
    
       Command Options         0000000r
    
                               r = response requested.  When set, the Realtime
    
                               Control Microcode provides command handler
    
                               notification that this command has completed via
    
                               a Move Response.  When clear, the requesting task
    
                               has no way of knowing when the command
    
                               completed.
    
       Target processor ID     CARDID of the Realtime Control Microcode to
    
                               process the command (normally the same as source
    
                               processor ID).
    
       Target task ID          0000h (Realtime Control Microcode).
    
       Source processor ID     CARDID of requesting task's processor.
    
       Source task ID          Source task number.
    
       Data byte count         Number of bytes to move.
    
       Data value 1            CARDID of target
    
       Least-significant byte  buffer
    
       Data value 1            CARDID of source
    
       Most-significant byte   buffer
    
       Data address 1          Destination buffer
    
                               (32-bit physical address)
    
       Data address 2          Source buffer
    
                               (32-bit physical address)
    
    
    
     EXIT:
    
       Completion code         00h Request block available.
    
                               01h Target processor not functioning
    
                                   or not present.
    
                               02h Target processor is not a peer
    
                                   processor.
    
                               03h Target processor is not loaded.
    
                               04h Target processor was suspended due
    
                                   to system unit re-IPL.
    
                               05h Target processor is in error state.
    
                               06h Target processor is not in the peer
    
                                   processor table.
    
                               07h Wait option was specified in a call
    
                                   from an interrupt handler.
    
                               08h Non-valid command.
    
                               7Fh Request pending.
    
       Request block ID        Unique block ID.
    
    
    
    

    Cancel Peer Request

    This command is issued to the Realtime Control Microcode to cancel a previously issued peer request. It can only be issued to the Realtime Control Microcode on the requesting task's card.

    A request cannot be cancelled once it is placed into the fixed queue area. The cancel request is immediately processed to completion. It is impossible to cancel a cancel request.

    If the cancelled request block requested an acknowledge, it is returned to the original requestor via its command handler with a completion code of A2h, request canceled.

    
    
    
     ENTRY:
    
       Command                 03h
    
       Peer Request Options    0000 0maw
    
                               m = multiple block request.  When set, this is
    
                               the first block of a multiple block request.
    
                               a = acknowledge requested.  When set, provides
    
                               command handler notification when the command
    
                               is delivered to the target processor/task.  For
    
                               best performance, this bit should be 0.
    
                               w = wait requested.  This bit is a "don't care"
    
                               for this command
    
       Command Options         0000000r
    
                               r = response requested.  When set, Realtime
    
                               Control Microcode provides command handler
    
                               notification that this command has completed via a
    
                               Cancel Response.  When clear, the requesting task
    
                               has no way of receiving the command completion
    
                               status.
    
       Target processor ID     CARDID of source
    
       Target task ID          0000h (Realtime Control Microcode)
    
       Source processor ID     CARDID of source
    
       Source task ID          Source task number
    
       Data value 1            Request block ID to cancel
    
    
    
     EXIT:
    
       Completion code         00h Request block available
    
                               01h Target processor not functioning
    
                                   or not present.
    
                               02h Target processor is not a peer
    
                                   processor.
    
                               03h Target processor is not loaded.
    
                               04h Target processor was suspended due
    
                                   to system unit re-IPL.
    
                               05h Target processor is in error state.
    
                               06h Target processor is not in the
    
                                   peer processor table.
    
                               07h Wait option was specified in a call from
    
                                   an interrupt handler.
    
                               08h Non-valid command
    
    
    
    

    Peer Ready

    This command is sent to the system unit by the Realtime Control Microcode when it has updated its peer processor table entry and wishes to notify other peers of its existence. It is also sent from the system unit to the peer processors so that they may update their copies of the peer table with the new status of the adapter. The system unit also sends a Peer Ready after a soft IPL. This command cannot be issued by an application task.

    The Peer Ready request block is defined as follows.

    
     ENTRY:
    
       Command                 01h
    
       Peer Option Flags       00h
    
       Command Option Flags    00h
    
       Target Processor ID     CARDID of target processor
    
       Target Task ID          0000h
    
       Source Processor ID     CARDID of source processor
    
       Source Task ID          0000h
    
       Data Value 1            Processor ID now ready
    
       Most-Significant Byte
    
       Data Address 1          When the source processor ID is
    
                               that of the system unit and
    
                               data value 1 is not equal to the
    
                               target processor ID, this field
    
                               contains the physical address of
    
                               the transmit fixed Q of the proc-
    
                               essor ID contained in data value 1.
    
                               When the source processor ID is
    
                               that of the system unit and
    
                               data value 1 is equal to the
    
                               target processor ID, this field is
    
                               not defined.
    
                               When the target processor ID is the
    
                               system unit, this field contains
    
                               the physical address of this card's
    
                               peer processor table.
    
       Data Address 2          When the source processor ID is
    
                               that of the system unit and
    
                               data value 1 is not equal to the
    
                               target processor ID, this field contains
    
                               the physical address of the receive fixed
    
                               Q of the processor ID contained in data
    
                               value 1.
    
                               When the source processor ID is that
    
                               of the system unit and data value 1 is
    
                               equal to the target processor ID, this
    
                               field is not defined.
    
                               When the target processor ID is the
    
                               system unit, this field is not defined.
    
    

    Peer Reset

    This command is sent to the Realtime Control Microcode on peer adapters from the system unit when a peer processor is about to be reset. The Realtime Control Microcode updates the status of the reset adapter in its copy of the peer table and aborts any pending peer requests with the reset peer. The system unit support issues this command to all peer adapters and waits for an acknowledgment from each adapter before issuing the reset. The wait for peer acknowledgment is subject to a timeout.

    The peer reset request block is defined as follows.

    
    
    
    Command                    00h
    
    Peer Option Flags          02h
    
    Command Option Flags       00h
    
    Target Processor ID        CARDID of target
    
    Target Task ID             0000h
    
    Source Processor ID        FFh
    
    Source Task ID             0000h
    
    Data Value 1               CARDID about to reset
    
    Most-Significant Byte
    
    

    Peer Request Responses

    Peer request responses are notifications that a command has been completed by the Realtime Control Microcode. A peer request command may or may not support responses. If it does, a response is provided when the response bit in the command options field is set. The requesting task receives response notification via its command handler as if it was an incoming command.

    The Realtime Control Microcode supports the following responses.

    Move Data Response

    This response is returned when a Move Data command specifies a response in the command options field.

    
    
    
     ENTRY:
    
       Command                 82h
    
       Peer Request Options    Undefined
    
       Command Options         Undefined
    
       Target processor ID     CARDID of Move command requestor
    
       Target task ID          Task number of Move command requestor
    
       Source processor ID     CARDID of Move command target
    
       Source task ID          Task number 0 (Realtime Control Microcode)
    
       Data byte count         Return Code
    
                               0000h = Move Command successful
    
                               0001h = Source/Target buffer processor ID
    
                                       not in peer processor table
    
                               0002h = Non-valid source/target buffer
    
                                       processor ID
    
                               0003h = Data byte count not valid
    
                               0004h = Insufficient storage for micro
    
                                       channel transfer
    
                               0005h = Source/target buffer processor
    
                                       not loaded or suspended
    
                               0006h = Micro channel I/O error
    
       Data value 1            Request block ID of Move Data command
    
       Data address 1          Undefined
    
       Data address 2          Undefined
    
    
    
     EXIT:
    
       No exit parameters defined
    
    
    
    

    Cancel Peer Response

    This response is returned when a Cancel Peer Request command specifies a response in the command options field.

    
     ENTRY:
    
       Command                 83h
    
       Peer Request Options    Undefined
    
       Command Options         Undefined
    
       Target processor ID     CARDID of Cancel Peer Request command
    
                               requestor
    
       Target task ID          Task number of Cancel Peer Request
    
                               command requestor
    
       Source processor ID     CARDID of Cancel Peer Request command
    
                               requestor
    
       Source task ID          Task number 0 (Realtime Control Microcode)
    
       Data byte count         Return Code
    
                               0000h = Command successful
    
                               0001h = Request block not found
    
       Data value 1            Request block ID of Cancel Peer Request
    
                               command
    
       Data address 1          Undefined
    
       Data address 2          Undefined
    
    
    
     EXIT:
    
       No exit parameters defined
    
    

    Peer Services Communications

    Peer services use a data structure called the fixed queue to transmit and receive peer request blocks from other peers (and the system unit). Each peer adapter contains one transmit fixed queue and one receive fixed queue for each other peer adapter and the system unit. The structure of the fixed queue is shown as follows:

    
    +---------------------------------------------------------------------+
    
    
    
    | Peer Fixed Queue                                                    |
    
    
    
    +----------+-------------+--------------------------------------------+
    
    
    
    | Offset   | Field Name  | Description                                |
    
    
    
    +----------+-------------+--------------------------------------------+
    
    | 00h-03h  | QHEAD       | FIFO queue head (80186 logical address)    |
    
    +----------+-------------+--------------------------------------------+
    
    | 04h-07h  | QTAIL       | FIFO queue tail (80186 logical address)    |
    
    +----------+-------------+--------------------------------------------+
    
    | 08h-0Bh  | NEXTFIXQ    | Next fixed queue pointer                   |
    
    +----------+-------------+--------------------------------------------+
    
    | 0Ch      | STAT        | Fixed queue status                         |
    
    +----------+-------------+--------------------------------------------+
    
    | 0Dh      | INDEX       | Index into peer processor table            |
    
    +----------+-------------+--------------------------------------------+
    
    | 0Eh-0Fh  | FQSIZE      | Fixed queue size (max number of entries)   |
    
    +----------+-------------+--------------------------------------------+
    
    | 10h-11h  | FQBUSY      | Fixed queue busy flag                      |
    
    +----------+-------------+--------------------------------------------+
    
    | 12h-13h  | INTPEND     | Fixed queue interrupt pending flag         |
    
    +----------+-------------+--------------------------------------------+
    
    | 14h-15h  | FQCOUNT     | Fixed queue pending count (entries)        |
    
    +----------+-------------+--------------------------------------------+
    
    | 16h-xxh  | FQREQBLK    | Fixed queue peer request blocks            |
    
    +----------+-------------+--------------------------------------------+
    
    

    The following sequence outlines the transmission of a peer request block from task A on adapter A to task B on adapter B with no acknowledgment requested:

    1. Task A calls peer services on adapter A with a peer request block to send to task B.

    2. Adapter A peer services copies the peer request block into its transmit fixed queue for adapter B.

    3. Adapter A peer services copies the peer request block and status information from the adapter B transmit fixed queue on its card to the adapter A receive fixed queue on adapter B.

    4. Adapter A peer services interrupts adapter B to notify its peer services that there is an entry on its adapter A receive fixed queue.

    5. Adapter B peer services calls task B's command handler with a pointer to the peer request block.

    6. Task B's command handler copies whatever information it needs from the peer request block and returns (if an acknowledgment was requested, the peer request block completion code must be set prior to returning).

    7. Adapter B peer services updates status information in its adapter A receive fixed queue and the adapter B transmit fixed queue on adapter A.

    8. Adapter B peer services interrupts adapter A to notify its peer services that the operation is complete.

    The preceding example assumes that the transmit fixed queue for adapter B was not already busy when task A issued its peer request. If it is busy, peer services queues the peer request block until the transmit fixed queue becomes available. Note that if multiple peer request blocks are queued for adapter B, they are all copied to the fixed queue (assuming that it is large enough) and sent to adapter B in one fixed queue transmit operation.

    Peer Services Initialization

    The peer processor table contains the information that allows peer processor communications. It consists of a peer table entry for the system unit and each peer adapter. The system unit and each peer adapter maintains its own copy of the peer processor table. The following sequence indicates the initialization process for an adapter which supports peer services.

    1. During initialization, the Realtime Control Microcode copies the system unit peer processor table to its own data area.

    2. The Realtime Control Microcode allocates storage for fixed queues for the system unit and other peers in its storage.

    3. The Realtime Control Microcode updates its copy of the peer processor table with pointers to its transmit and receive fixed queues.

    4. The Realtime Control Microcode sends a Peer Ready command to the system unit. This command contains the address of the Realtime Control Microcode's copy of the peer processor table.

    5. The system unit copies the fixed queue information from the Realtime Control Microcode's copy into its own copy of the peer processor table.

    6. The system unit sends a Peer Ready command to any peer adapters which were already initialized. This command contains the addresses of the transmit and receive fixed queues for the just initialized adapter.

    7. The system unit sends a Peer Ready command to the just initialized adapter for all other peer adapters that are already initialized.

    This preceding process is repeated for peer adapters until all have been initialized.

    
    +--------------------------------------------------------+
    
    
    
    | Peer Processor Table                                   |
    
    
    
    +-------------+------------------------------------------+
    
    
    
    | Offset      | Field Name                               |
    
    
    
    +-------------+------------------------------------------+
    
    | 00h-9Bh     | System unit peer table entry             |
    
    +-------------+------------------------------------------+
    
    | 9Ch-xxh     | Card 0 thru N peer table entry array     |
    
    +-------------+------------------------------------------+
    
    
    
    
    
    +--------------------------------------------------------+
    
    
    
    | Peer Table Entry                                       |
    
    
    
    +-------------+------------------------------------------+
    
    
    
    | Offset      | Field name                               |
    
    
    
    +-------------+------------------------------------------+
    
    | 00h-01h     | Status                                   |
    
    +-------------+------------------------------------------+
    
    | 02h-03h     | ProcessorType                            |
    
    +-------------+------------------------------------------+
    
    | 04h-05h     | Base@                                    |
    
    +-------------+------------------------------------------+
    
    | 06h-09h     | Window@                                  |
    
    +-------------+------------------------------------------+
    
    | 0Ah-0Dh     | WindowSize                               |
    
    +-------------+------------------------------------------+
    
    | 0Eh         | ArbLevel                                 |
    
    +-------------+------------------------------------------+
    
    | 0Fh         | FQSize                                   |
    
    +-------------+------------------------------------------+
    
    | 10h         | Proc ID                                  |
    
    +-------------+------------------------------------------+
    
    | 11h-1Bh     | Reserved(12)                             |
    
    +-------------+------------------------------------------+
    
    | 1Ch-5Bh     | Transmit fixed queue pointer array(16)   |
    
    +-------------+------------------------------------------+
    
    | 5Ch-9Bh     | Receive fixed queue pointer(16)          |
    
    +-------------+------------------------------------------+
    
    

    The values of the various peer processor table variables are as follows:

    Peer Services Recovery

    Peer Adapter Failure

    Failure of other peer adapters can be detected by time-outs and parity errors. When the Realtime Control Microcode detects a time-out error, it sets that peer adapter's peer processor table status to error. All pending requests for that peer are returned to the requestor with a target processor time-out error. Any outstanding acknowledgments are sent to the requestor with a delivery time-out error code. Subsequent requests are rejected with a target processor time-out error code until a Peer Ready command is received for the failed peer adapter.

    Parity errors can occur on either the bus master or the slave peer adapter. When a parity error occurs, Realtime Control Microcode on the source adapter attempts to recover by retrying the requested operation. If unsuccessful, it performs the actions shown in the following table.

    
    
    
    +---------------------------------------------------------------------+
    
    
    
    | Bus Master Parity Error Actions                                     |
    
    
    
    +-----------------------------+---------------------------------------+
    
    
    
    | Parity Error Source         | Failure Action                        |
    
    
    
    +-----------------------------+---------------------------------------+
    
    | Local DRAM Read             | Return error to requesting task or    |
    
    |                             | Realtime Control Microcode as         |
    
    |                             | appropriate.  If error occurred in    |
    
    |                             | Realtime Control Microcode data       |
    
    |                             | area, disable peer services.          |
    
    +-----------------------------+---------------------------------------+
    
    | Remote (slave) DRAM Read    | Return error to requesting task.      |
    
    +-----------------------------+---------------------------------------+
    
    

    System Unit IPL

    If a system unit re-IPL occurs, the Realtime Control Microcode marks all peer or slave adapters as "suspended" in its peer processor table. All pending requests for other adapters are returned to the requestor with a target processor suspended error code. Any outstanding acknowledgments are sent to the requestor with a target processor suspended error code. Subsequent requests are rejected with a target processor suspended error code until a Peer Ready command is received for the system unit.

    Command Interrupt Handling for Peer Requests

    Previously, tasks received notification of commands from the system unit via their command handler and BCB. In addition, requests from peer processors are now also presented to the command handler. A peer request block can be passed to a command handler because a request has arrived from another peer task or as an acknowledgment to a previous request sent by this task.

    To distinguish between older style command interrupts and the newer peer request interrupts, a value is passed to the command handler in the CL register. This is transparent to older applications because they only receive system unit interrupts and do not expect any values in the registers upon entry.

    Register CL contains a value of 00h upon entry to the command handler for compatibility interrupts from the system unit. For peer requests, ES:BX contains a pointer to the first of one or more peer request blocks destined for the owner of the command handler. Register CL contains a count of the number of contiguous peer request blocks. When called, the command handler must copy whatever information it needs from the peer request block(s) into task storage. If a peer request block is an acknowledgment, the most-significant bit of the completion code field is set to 1. If a peer request block is not an acknowledgment or a response, the command handler must set the completion code field to a value in the range of C0h-DFh indicating successful delivery. If it cannot accept the peer request block, it must set the completion code field to a value in the range of E0h-FFh indicating rejection of the request block.

    For compatibility, the BCB and its structures remain dedicated to system-unit-to-card communications via existing commands.

    Disabling Peer Services

    Realtime Control Microcode Version 2.01 allows a user to disable peer services by specifying an optional parameter of 1 (one) when invoking either of the system support application loader utilities. For example:

    
         ICALOAD 0 ICARCM.COM 0   ( 1
    
    

    (Refer to the Realtime Interface Co-Processor DOS Support Version 1.02 User's Guide or the OS/2 Support Version 1.03 User's Guide for information on the operation of the application loader utilities.)

    This parameter causes Realtime Control Microcode to bypass the building of peer related tables. The memory normally used by these tables, remains in the free storage pool. Calls to the peer request SVI return an access denied error.

    This feature is not available on versions of Realtime Control Microcode prior to Version 2.01.


    Additional Task Services

    Certain services are provided via IBM supported software that perform miscellaneous functions frequently required by an application task. These services are provided to make task writing easier.

    Associated Interface Modules

    
    ----------------------------------------------------------
    
     Type            Invocation      Name
    
    ----------------------------------------------------------
    
     PROM Service    INT B6h         SEG2PAGL
    
    
    
     PROM Service    INT B8h         PAG2SEGL
    
    
    
     PROM Service    INT C0h         Pointer to EBCDIC-
    
                                     ASCII table
    
    
    
     PROM Service    INT C2h         EBC2ASC
    
    
    
     PROM Service    INT C4h         ASC2EBC
    
    
    
     PROM Service    INT C6h         ADDINTRA
    
    
    
     PROM Service    INT C8h         REMINTRA
    
    
    
     PROM Service    INT CAh         ADDINTER
    
    
    
     PROM Service    INT CCh         REMINTER
    
    
    
     SVC             INT 56h,        READVEC
    
                     AH = 42h
    
    
    
     SVC             INT 56h,        QFREEST
    
                     AH = 49h
    
    
    
     Service         INT 60h         SEG2PAG
    
     Interrupt
    
    
    
     Service         INT 62h         PAG2SEG
    
     Interrupt
    
    
    
     Service         INT 70h         TRANSEG
    
     Interrupt
    
    

    Asynchronous Error Handling

    Asynchronous errors are those errors or exceptional conditions that occur unexpectedly. Because they may occur at any given time, the Realtime Control Microcode must continuously monitor for their occurrence. In contrast, an SVC error is not asynchronous because it may occur only when the call is processed. Therefore, the possibility of its occurrence can be anticipated, and appropriate error handling is done at the time the call finishes executing.

    Asynchronous error and exception conditions are detected by the Realtime Control Microcode. Handling of the error is performed by the Realtime Control Microcode, unless a task makes special arrangements before the error occurrence to handle the error if it occurs. Occurrence of an asynchronous error causes the Realtime Control Microcode to jump to the appropriate error handler interrupt vector in the following list.

    This section describes how asynchronous error and exception conditions are handled by the Realtime Control Microcode and application tasks that execute on the co-processor adapter.

    List of Asynchronous Error Conditions

    Types of error conditions that are detected are:

    
    +---------------------------------+-----------------+-----------------+
    
    
    
    | Error Condition                 | Multiport       | Portmaster      |
    
    |                                 | Adapter,        | Adapter/A       |
    
    |                                 | Model 2         | Interrupt #     |
    
    |                                 | Interrupt #     |                 |
    
    
    
    +---------------------------------+-----------------+-----------------+
    
    | Divide by Zero Interrupt        | EFh             | EFh             |
    
    +---------------------------------+-----------------+-----------------+
    
    | Bounds Error Interrupt          | F1h             | F1h             |
    
    +---------------------------------+-----------------+-----------------+
    
    | INTO Interrupt                  | F3h             | F3h             |
    
    +---------------------------------+-----------------+-----------------+
    
    | Operation code check            | F5h             | F5h             |
    
    | (also escape (ESC)              |                 |                 |
    
    | operation code check)           |                 |                 |
    
    +---------------------------------+-----------------+-----------------+
    
    | Watchdog timer expiration       | F7h             | F7h             |
    
    +---------------------------------+-----------------+-----------------+
    
    | Co-processor adapter parity     | F9h             | F9h             |
    
    | error                           |                 |                 |
    
    +---------------------------------+-----------------+-----------------+
    
    | DAC error interrupt             | N/A             | EBh             |
    
    +---------------------------------+-----------------+-----------------+
    
    | PS/2 channel check error        | N/A             | FFh             |
    
    +---------------------------------+-----------------+-----------------+
    
    | Translate table error           | N/A             | EDh             |
    
    +---------------------------------+-----------------+-----------------+
    
    | Lost refresh error              | FFh             | N/A             |
    
    +---------------------------------+-----------------+-----------------+
    
    | Non-maskable interrupt from     | FBh             | FBh             |
    
    | system unit                     |                 |                 |
    
    +---------------------------------+-----------------+-----------------+
    
    | Compare degate detect           | FDh             | FDh             |
    
    | (system unit initial program    |                 |                 |
    
    | load detect)                    |                 |                 |
    
    +---------------------------------+-----------------+-----------------+
    
    | Extended non-maskable interrupt | BDh             | BDh             |
    
    | error                           |                 |                 |
    
    +---------------------------------+-----------------+-----------------+
    
    

    Realtime Control Microcode Asynchronous Error Handling

    When one of the preceding asynchronous conditions is detected by the Realtime Control Microcode, the condition is handled in the following manner.

    The Realtime Control Microcode executes an INT EFh-FEh (depending on the error), and each task that acquired the associated interrupt vector is given control by the Realtime Control Microcode. Each task has the option of handling the error itself in whole or in part or letting the Realtime Control Microcode handle the error. Unless otherwise specified, the Realtime Control Microcode processes the error and checks to determine if an interrupt handler was executing. If not, the current task in execution is stopped, and the Realtime Control Microcode performs the following:

    If an interrupt handler was executing, the Realtime Control Microcode cannot determine which task was executing; therefore, all tasks are suspended by the Realtime Control Microcode, regardless of their permanent status.

    Each error condition is described as follows:

    Divide-by-Zero Interrupt

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector EFh. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    Bounds Error Interrupt

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector F1h. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    INTO Interrupt

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector F3h. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    Operation Code Check Error

    If an operation code check error occurs, the Realtime Control Microcode gives control to any task that has acquired interrupt vector F5h. When control is returned to the Realtime Control Microcode, if AL = 00, no further action is taken; otherwise, the Realtime Control Microcode's error bit in the primary status byte in the interface block is set. The secondary status of the Realtime Control Microcode includes the address of the byte after the byte with the bad opcode. This should be sufficient for most programmers to start their debug. The system unit is interrupted with the error notification.

    Watchdog Timer Expiration

    For watchdog timer errors, the Realtime Control Microcode gives control to any task that has acquired interrupt vector F7h. When control is returned to the Realtime Control Microcode, if AL = 00, no further action is taken; otherwise, all tasks are suspended by the Realtime Control Microcode. The system unit is interrupted by hardware.

    Co-Processor Adapter Storage Parity Check Error

    If a co-processor adapter parity error occurs, the Realtime Control Microcode gives control to any task that has acquired vector F9h. When control is returned to the Realtime Control Microcode, if AL = 00h, no further action is taken, and the Realtime Control Microcode continues normal processing. If AL is non-zero, or no task has acquired vector F9h, the Realtime Control Microcode secondary status is as follows:

    DAC Error Interrupt

    If a DAC error occurs, the Realtime Control Microcode gives control to any task that has acquired vector EBh. When control is returned to the Realtime Control Microcode, if AL = 00h, no further action is taken and the Realtime Control Microcode continues normal processing.

    If AL is non-zero, or no task has acquired vector EBh, the Realtime Control Microcode suspends:

    1. The current task in execution if the DAC occurred as a result of an 80186 access and an interrupt handler was not executing.

    2. All tasks if the DAC occurred as a result of an 80186 access and an interrupt handler was executing.

    3. The task owning the DMA channel if the DAC occurred as a result of a DMA/Peripheral Interface Controller channel access.

    The system unit is notified as follows:

    1. Realtime Control Microcode secondary status is set as follows:
    2. The Realtime Control Microcode's primary status error and status available bits are set.
    3. The Realtime Control Microcode sets INTID = FEh and interrupts the system unit.

    Channel Check Error

    Channel check errors can occur as a result of slave card read parity errors. Slave card read errors are reported by the slave to the bus master via the channel check signal on the micro channel.

    Realtime Control Microcode peer services will retry channel check errors if it initiated the channel operation. If the retry operations fail, an error code is returned to the requestor. Realtime Control Microcode gives control to any task that has acquired vector FFh, with register AX set as follows:

    For Realtime Control Microcode 2.0, secondary status is set as follows. (For Realtime Control Microcode Version 2.01, see the next page.)

    For Realtime Control Microcode Version 2.01, the error is signaled to the system unit as follows:

    1. Realtime Control Microcode's secondary status is set as follows:

    2. Realtime Control Microcode's primary status error and status available bits are set.

    3. Realtime Control Microcode sets INTID = FEh and interrupts the system unit.

    Translate Table Error

    The translate table error will occur when a task attempts to access the expanded memory page frame address when no expanded memory pages are mapped. When a translation table error occurs, the Realtime Control Microcode gives control to any task that has acquired vector EDh. When control is returned to the Realtime Control Microcode, if AL = 00h, no further action is taken, and the Realtime Control Microcode continues normal processing.

    If AL is non-zero or no task has acquired vector EDh, the Realtime Control Microcode's secondary status is set as follows:

    Extended Non-maskable Interrupt Error

    This capability allows adapters similar to Portmaster Adapter/A to signal events to an application task via an NMI. When the Realtime Control Microcode receives an NMI, it passes control to any task that has acquired vector BFh. Interrupts are disabled when the task receives control.

    Non-Maskable Interrupt from the System Unit

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector FBh. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    Compare Degate Detect

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector FDh. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    System Unit Channel Check or Lost Refresh Detect

    The Realtime Control Microcode gives control to any task that has acquired interrupt vector FFh. No further action is taken, and the Realtime Control Microcode continues normal function processing.

    Application Task Error Handling

    If a task needs to handle any of these errors, the mechanism for doing so is to acquire the specific user interrupt vector for that error. If the error occurs, the Realtime Control Microcode passes control through that interrupt vector before it processes the interrupt. Your application task can expect interrupts to be enabled and all non-maskable interrupts (NMIs) to be masked off when it receives control. The Realtime Control Microcode handles the unmasking of NMIs when control is passed back from your task. If your task does not need the Realtime Control Microcode to do any further error handling, it should set the AL register to 0. It is permissible for the task to do some processing and still request that the Realtime Control Microcode completes processing the error.

    Associated Interface Modules

    None.


    Chapter 13. Interrupt Vector Table Map for the Portmaster Adapter/A and Multiport Adapter, Model 2

    This chapter provides information about the Interrupt Vector Map for the Realtime Interface Co-Processor Portmaster Adapter/A and the Realtime Interface Co-Processor Multiport Adapter, Model 2. (For related information for the Realtime Interface Co-Processor, the Realtime Interface Co-Processor Multiport, and the Realtime Interface Co-Processor Multiport/2, see Chapter 11. "Interrupt Vector Table Map for the Realtime Interface Co-Processor, Multiport, and Multiport/2 Adapters".)

    To support the new hardware available on Portmaster Adapter/A, the interrupt vector table has been remapped. All PROM and Realtime Control Microcode interrupt vectors remain unchanged to preserve compatibility with existing applications. Each of the first eight ports has six separate interrupt vectors (transmit, receive, error, special receive condition, and two DMA terminal counts).

    The remaining 24 ports are grouped on vectors, and a status register must be used to determine the exact source of the interrupt. A single vector is allocated for each communications chip (one for every two ports), and a single vector is allocated for each group of 16 DMA channels. A vector is defined for ports A and B of CIOs 0 through 7.

    Four vectors are also dedicated to the timers on each of the eight CIOs. A new vector (CEh) is dedicated to new PROM services. New Realtime Control Microcode service interrupts are grouped on interrupt 72h. New user-requestable error interrupts are also allocated for extended NMI, DAC, and translate table errors.

    The user-requestable interrupt vectors were formerly all the odd vectors in the range 21h-FFh. The new interrupt mapping defines odd vectors 71h-BDh and EBh-FFh as user-requestable. The interrupts reserved for interface boards (7Ch and 7Eh) are also user-requestable.

    
    
    
      Int No.   Function
    
      ___________________________________________________________
    
    
    
      00        Divide error
    
      01        Single step
    
      02        NMI
    
      03        Breakpoint
    
      04        INTO detected overflow
    
      05        Array bounds exception
    
      06        Opcode check
    
      07        Escape opcode exception
    
    
    
      08        80186 Timer 0 (software timer control)
    
      09        Reserved
    
      0A        80186 DMA 0
    
      0B        80186 DMA 1
    
      0C        INT 0 (shared storage interface chip)
    
      0D        Reserved by Intel
    
      0E        INT 2
    
      0F        Reserved by Intel
    
    
    
      10        Reserved by Intel
    
      11        Reserved by Intel
    
      12        80186 Timer 1 (Time slice control)
    
      13        80186 Timer 2 (80186 Timer 0 and 1 pre-scaler)
    
      14        Reserved by Intel
    
      15        Reserved by Intel
    
      16        Reserved by Intel
    
      17        Reserved by Intel
    
    
    
      18        Reserved by Intel
    
      19        Reserved by Intel
    
      1A        Reserved by Intel
    
      1B        Reserved by Intel
    
      1C        Reserved by Intel
    
      1D        Reserved by Intel
    
      1E        Reserved by Intel
    
      1F        Reserved by Intel
    
    
    
      20        DUSCC Port 0 receive -or- SCC Port 1 transmit
    
      21        DUSCC Port 0 transmit -or- SCC Port 3 transmit
    
      22        DUSCC Port 0 Rx/Tx status -or- SCC Port 1 ext status
    
    
    
      Int No.   Function
    
      ______________________________________________________________________
    
    
    
      23        DUSCC Port 0 ext or C/T status -or- SCC Port 3 ext status
    
      24        DUSCC Port 1 receive -or- SCC Port 1 receive
    
      25        DUSCC Port 1 transmit -or- SCC Port 3 receive
    
      26        DUSCC Port 1 Rx/Tx status -or- SCC Port 1 special rcv
    
      27        DUSCC Port 1 ext or C/T status -or- SCC Port 3 special rcv
    
    
    
      28        DUSCC Port 2 receive -or- SCC Port 0 transmit
    
      29        DUSCC Port 2 transmit -or- SCC Port 2 transmit
    
      2A        DUSCC Port 2 Rx/Tx status -or- SCC Port 0 ext status
    
      2B        DUSCC Port 2 ext or C/T status -or- SCC Port 2 ext status
    
      2C        DUSCC Port 3 receive -or- SCC Port 0 receive
    
      2D        DUSCC Port 3 transmit -or- SCC Port 2 receive
    
      2E        DUSCC Port 3 Rx/Tx status -or- SCC Port 0 special rcv
    
      2F        DUSCC Port 3 ext or C/T status -or- SCC Port 2 special rcv
    
    
    
      30        DUSCC Port 4 receive -or- SCC Port 5 transmit
    
      31        DUSCC Port 4 transmit -or- SCC Port 7 transmit
    
      32        DUSCC Port 4 Rx/Tx status -or- SCC Port 5 ext status
    
      33        DUSCC Port 4 ext or C/T status -or- SCC Port 7 ext status
    
      34        DUSCC Port 5 receive -or- SCC Port 5 receive
    
      35        DUSCC Port 5 transmit -or- SCC Port 7 receive
    
      36        DUSCC Port 5 Rx/Tx status -or- SCC Port 5 special rcv
    
      37        DUSCC Port 5 ext or C/T status -or- SCC Port 7 special rcv
    
    
    
      38        DUSCC Port 6 receive -or- SCC Port 4 transmit
    
      39        DUSCC Port 6 transmit -or- SCC Port 6 transmit
    
      3A        DUSCC Port 6 Rx/Tx status -or- SCC Port 4 ext status
    
      3B        DUSCC Port 6 ext or C/T status -or- SCC Port 6 ext status
    
      3C        DUSCC Port 7 receive -or- SCC Port 4 receive
    
      3D        DUSCC Port 7 transmit -or- SCC Port 6 receive
    
      3E        DUSCC Port 7 Rx/Tx status -or- SCC Port 4 special rcv
    
      3F        DUSCC Port 7 ext or C/T status -or- SCC Port 6 special rcv
    
    
    
      40        DUSCC Ports 8 and 9 -or- SCC Ports 8 and 9
    
      41        CIO Port 0
    
      42        DUSCC Ports A and B -or- SCC Ports A and B
    
      43        CIO Port 1
    
      44        DUSCC Ports C and D -or- SCC Ports C and D
    
      45        CIO Port 2
    
      46        DUSCC Ports E and F -or- SCC Ports E and F
    
      47        CIO Port 3
    
    
    
      48        DUSCC Ports 10 and 11 -or- SCC Ports 10 and 11
    
      49        CIO Port 4
    
      4A        DUSCC Ports 12 and 13 -or- SCC Ports 12 and 13
    
    
    
      Int No.   Function
    
      __________________________________________________________
    
    
    
      4B        CIO Port 5
    
      4C        DUSCC Ports 14 and 15 -or- SCC Ports 14 and 15
    
      4D        CIO Port 6
    
      4E        DUSCC Ports 16 and 17 -or- SCC Ports 16 and 17
    
      4F        CIO Port 7
    
    
    
      50        Echo 1
    
      51        CIO 4 Timer 3 (Hardware Timer #D)
    
      52        Echo 2
    
      53        CIO 4 Timer 2 (Hardware Timer #C)
    
      54        Echo 3
    
      55        CIO 4 Timer 1 (Hardware Timer #B)
    
      56        RCM SVC
    
      57        CIO 4 Timer Error Vector
    
    
    
      58        Debug 1
    
      59        CIO 5 Timer 3 (Hardware Timer #10)
    
      5A        Debug 2
    
      5B        CIO 5 Timer 2 (Hardware Timer #F)
    
      5C        Debug 3
    
      5D        CIO 5 Timer 1 (Hardware Timer #E)
    
      5E        Reserved (Programming Services)
    
      5F        CIO 5 Timer Error Vector
    
    
    
      60        SEG2PAGE
    
      61        CIO 6 Timer 3 (Hardware Timer #13)
    
      62        PAGE2SEG
    
      63        CIO 6 Timer 2 (Hardware Timer #12)
    
      64        POSTI
    
      65        CIO 6 Timer 1 (Hardware Timer #11)
    
      66        RESUMEI
    
      67        CIO 6 Timer Error Vector
    
    
    
      68        CANTIMEI
    
      69        CIO 7 Timer 3 (Hardware Timer #16)
    
      6A        GETELEM
    
      6B        CIO 7 Timer 2 (Hardware Timer #15)
    
      6C        ADDELEM
    
      6D        CIO 7 Timer 1 (Hardware Timer #14)
    
      6E        REMELEM
    
      6F        CIO 7 Timer Error Vector
    
    
    
      Int No.   Function
    
      ________________________________________________________
    
    
    
      70        TRANSSEG
    
      71        User-requestable (Trace Facility)
    
      72        Extended SVI
    
      73        User-requestable (Trace Facility)
    
      74        Logical Control Line Support
    
      75        User-requestable (Communications Services)
    
      76        Reserved
    
      77        Reserved
    
    
    
      78        Reserved
    
      79        Reserved
    
      7A        Reserved
    
      7B        User-requestable
    
      7C        Reserved
    
      7D        User-requestable
    
      7E        Reserved
    
      7F        User-requestable
    
    
    
      80        Echo 0 DMA Channel 0
    
      81        User-requestable
    
      82        Echo 0 DMA Channel 1
    
      83        User-requestable
    
      84        Echo 0 DMA Channel 2
    
      85        User-requestable
    
      86        Echo 0 DMA Channel 3
    
      87        User-requestable
    
    
    
      88        Echo 0 DMA Channel 4
    
      89        User-requestable
    
      8A        Echo 0 DMA Channel 5
    
      8B        User-requestable
    
      8C        Echo 0 DMA Channel 6
    
      8D        User-requestable
    
      8E        Echo 0 DMA Channel 7
    
      8F        User-requestable
    
    
    
      Int No.   Function
    
      ________________________________________________________
    
    
    
      90        Echo 0 DMA Channel 8
    
      91        User-requestable
    
      92        Echo 0 DMA Channel 9
    
      93        User-requestable
    
      94        Echo 0 DMA Channel A
    
      95        User-requestable
    
      96        Echo 0 DMA Channel B
    
      97        User-requestable
    
    
    
      98        Echo 0 DMA Channel C
    
      99        User-requestable
    
      9A        Echo 0 DMA Channel D
    
      9B        User-requestable
    
      9C        Echo 0 DMA Channel E
    
      9D        User-requestable
    
      9E        Echo 0 DMA Channel F
    
      9F        User-requestable
    
    
    
      A0        INTPCL
    
      A1        User-requestable
    
      A2        CCRESET
    
      A3        User-requestable
    
      A4        CCREGS
    
      A5        User-requestable
    
      A6        CIOREGS
    
      A7        User-requestable
    
    
    
      A8        CIOTMR
    
      A9        User-requestable
    
      AA        Reserved (formerly DMACONNECT)
    
      AB        User-requestable
    
      AC        DMASUPPORT
    
      AD        User-requestable
    
      AE        DMAREGS
    
      AF        User-requestable
    
      B0        DMASTOP
    
      B1        User-requestable
    
      B2        DMAADDR
    
      B3        User-requestable
    
      B4        Reserved
    
      B5        User-requestable
    
    
    
      Int No.   Function
    
      ________________________________________________________
    
    
    
      B6        SEG2PAGEL
    
      B7        User-requestable
    
    
    
      B8        PAGE2SEGL
    
      B9        User-requestable
    
      BA        Reserved
    
      BB        User-requestable
    
      BC        Reserved
    
      BD        Extended NMI (user-requestable)
    
      BE        Reserved
    
      BF        Reserved (remap of channel check)
    
    
    
      C0        Pointer to EBCDIC-ASCII tables
    
      C1        CIO Port 8
    
      C2        EBC2ASC
    
      C3        CIO Port 9
    
      C4        ASC2EBC
    
      C5        CIO Port A
    
      C6        ADDINTRA
    
      C7        CIO Port B
    
    
    
      C8        REMINTRA
    
      C9        CIO Port C
    
      CA        ADDINTER
    
      CB        CIO Port D
    
      CC        REMINTER
    
      CD        CIO Port E
    
      CE        PROM Services
    
      CF        CIO Port F
    
    
    
      D0        CIO 0 Timer 3 (Watchdog)
    
      D1        CIO 1 Timer 3 (Hardware Timer #4)
    
      D2        CIO 0 Timer 2 (Hardware Timer #1)
    
      D3        CIO 1 Timer 2 (Hardware Timer #3)
    
      D4        CIO 0 Timer 1 (Hardware Timer #0)
    
      D5        CIO 1 Timer 1 (Hardware Timer #2)
    
      D6        CIO 0 Timer Error Vector
    
      D7        CIO 1 Timer Error Vector
    
    
    
      D8        CIO 2 Timer 3 (Hardware Timer #7)
    
      D9        CIO 3 Timer 3 (Hardware Timer #A)
    
      DA        CIO 2 Timer 2 (Hardware Timer #6)
    
      DB        CIO 3 Timer 2 (Hardware Timer #9)
    
      DC        CIO 2 Timer 1 (Hardware Timer #5)
    
    
    
      Int No.   Function
    
      ___________________________________________________________
    
    
    
      DD        CIO 3 Timer 1 (Hardware Timer #8)
    
      DE        CIO 2 Timer Error Vector
    
      DF        CIO 3 Timer Error Vector
    
    
    
      E0        Reserved
    
      E1        Reserved
    
      E2        Reserved
    
      E3        Reserved
    
      E4        Reserved
    
      E5        Reserved
    
      E6        Reserved
    
      E7        Reserved
    
    
    
      E8        DUSCC Ports 18 and 19 -or- SCC Ports 18 and 19
    
      E9        Reserved
    
      EA        DUSCC Ports 1A and 1B -or- SCC Ports 1A and 1B
    
      EB        DAC Detected (user-requestable)
    
      EC        DUSCC Ports 1C and 1D -or- SCC Ports 1C and 1D
    
      ED        Translate Table Error (user-requestable)
    
      EE        DUSCC Ports 1E and 1F -or- SCC Ports 1E and 1F
    
      EF        Divide Error Exception (user-requestable)
    
    
    
      F0        Reserved
    
      F1        Array bounds exception (user-requestable)
    
      F2        Reserved
    
      F3        Interrupt on overflow exception (user-requestable)
    
      F4        Reserved
    
      F5        Invalid opcode error (user-requestable)
    
      F6        Reserved
    
      F7        Watchdog error detected
    
    
    
      F8        Reserved
    
      F9        Parity error detected (user-requestable)
    
      FA        Reserved
    
      FB        NMI from system unit (user-requestable)
    
      FC        Reserved
    
      FD        Compare Degate Detected (user-requestable)
    
      FE        Diagnostic test subroutine call
    
      FF        Channel check (user-requestable)
    
    

    Last modified: March 25, 1999