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Rough as heck. @8FEC.ADF -
IBM ARTIC960 Co-Processor Platform Adapter (ARTIC960
PCI is the PCI version...)
C8FEC.ADF - Init file for @8FEC.ADF 9mc105.exe ARTIC960 Startup/Option Diskette V1.05 r9mc105.txt ARTIC960 Startup/Option Diskette V1.05 README 193-258 IBM ARTIC960 CO-PROCESSOR PLATFORM ARTIC960 Support for AIX ARTIC960 Support for AIX Developers Kit ARTIC960 Support for AIX Supplemental Diskette ARTIC960 Support for WinNT ARTIC960 Support for WinNT Developers Kit MANUALS ARTIC 960/ARTIC 960PCI Co-Processor Guide to Ops Supplement (lost!) e9er.pdf ARTIC STREAMS Support WAN Driver Interface Reference ARTIC960 Co-Processor Platforms Hardware Technical Reference ARTIC960 Programmer's Guide ARTIC960 Programmer's Reference ARTIC960 STREAMS Environment Reference ARTIC960 Co-Processor Platforms Application Interface Board Developer's Guide, (not found!) e9eqbase.pdf
Realtime Interface Co-Processor C
Language Support README 9as122o.txt Installation instructions for IBM ARTIC960 OS/2 ANDIS MAC Device Driver Ver 1.2.2Cashing in on the ARTIC960 caches IBM ARTIC Legacy Downloads qCF
SOFTWARE FOR ARTIC Quadron's qCF is a C-language
software development and enhanced runtime support
package for ARTIC cards ARTIC960 Base Board P/N
06H4651, FRU 61G2916 
U1 - 80960Cx -80960CA 25MHz (initial production) replaced by 80960CF (later production). The CA and CF are register compatible. U2, 4 Instruction memory (DRAM SOJ modules) 1 or 4MB, 1 to 3 wait states (could be ordered with 4MB!) U14 34G1519 Brighton Memory Bus controller (plus ECC!) Brighton Component Specification (Used on i960 boards) U18 34G1521 Miami System Bus Interface Miami Component Specification (used on i960 boards) U19 - Pericom P174FCT - Fast CMOS Octal D Flip-Flop with Master Reset Datasheet U20 06H3691 EPROM? U25 - 72 pin SIMM, (mine had a 1Mx40, ECC, 80nS SIMM in it. LED Code The LED flashing sequence may be particularly useful for errors that occur very early on in Preliminary POST, thus preventing notification via the ISP Register. The No. of Flashes defines a period of consecutive visible flashes followed by a pause. This pattern is repeated indefinitely.
What is the purpose of the light on top of the ARTIC card? The light on the ARTIC card indicates the status of the ARTIC POST routines. The light normally comes on during POST (power on or reset), and goes off after successful completion of POST. If the light remains on, an error has been detected and an error code will be in task 0's secondary status buffer. A flashing light indicates a memory error on the card (since the error code can not be reported via memory). One other difference in reset between Micro Channel and PCI systems is that Ctrl+Alt+Del does not reset adapters in PCI systems. J3 Clock Signal on ARTIC960 Co-Processor Platform (Micro Channel)  The ARTIC960 supplies a clock signal (25MHz) to the AIB. This signal must be terminated at all times. Normally, the AIB circuitry terminates this signal. The ARTIC960 has a three-pin jumper (J3), which provides an on-card resistance-capacitance (RC) termination for the clock. If you do not have an AIB installed, J3 is jumpered 2-3 to terminate the clock signal on the ARTIC960. When an AIB is installed, J3 is jumpered 1-2, which is a "no-connect" position for the on-card termination circuitry, and allows the termination to take place using the AIB circuitry. NOTE: On this ARTIC960 with an installed AIB, J3 was jumpered for 3-2, which is supposedly for Termination. 6 Port V.36 AIB FRU 11H3795 (52G0985?) 
The oscillator frequency supplied to the DUSCCs is
14.745 MHz. U9,11,91 SC26C562C1A Dual universal serial communications controller (DUSCC) Datasheet DS36950 Quad Differential Bus Transceiver Datasheet lT1141A - Advanced Low Power 5V RS232 Drivers/Receivers with Small Capacitors Datasheet Components:
# 6941 ... cable, 4-port EIA-232 61G2918
# 6944 ... cable, 4-port V.36 61G2933 For the '94 RS/6000 versions, memory supported has
dropped to the 1, 4, or 8MB SIMM. Included in this announcement is a high-speed 4-Port
multi-interface Application Interface Board (AIB). The
AIB offers either EIA-232D (asynchronous), or EIA-530
(RS422), or ISO 4903 (X.21) or ISO 4902 (V.36)
electrical interfaces for communications applications.
The selection of the specific interface is achieved by a
matching cable (4 ports of 232 or 4 ports of 422 or 4
ports of X.21 or 4 ports of V.36). A developer's kit is offered that provides AIB design information, sample programs, a programmer's guide/reference, and a hardware technical reference manual. As part of the developer's kit a Developer's Assistance Program (DAP) is provided for parties who will be developing their own software applications and/or designing their own application interface board. The ARTIC960 DAP Limitations The ARTIC960 adapter requires a 32-bit slot in the following Micro Channel machines There is no limitation on the quantity of ARTIC960 cards per system other than 32-bit Micro Channel long slot availability and the amount of power furnished by the system. A typical ARTIC960 adapter, without the AIB, draws 12.5 watts of 5VDC power. The Multi-interface AIB draws an additional 3.7 watts. Limitations RS/6000 There is a limitation of 5 IBM ARTIC960 coprocessor with the supplied driver in all models except Machine Type 7009 Model C10 which has a limit of 2. Memory The adapter is designed with two memory banks. The instruction memory is 1MB large and is soldered in place. The other memory bank or data memory (also referred to as "packet") is provided in the form of a selectable pluggable SIMM package. The SIMM sizes are 1, 4, 8, and 16MB, with the card designed to accept a 32MB SIMM. A SIMM must be installed for the ARTIC960 to operate. NOTE: I have an ARTIC960 with a 6 port V.36 AIB, and the SIMM is a 4M ECC SIMM. 68X6356 1Mx40 E 80nS, 5v @8FECH ARTIC960 Co-Processor Platform Adapter Modify the ADF file so that all features are "disabled" and remove the ability to disable channel check sources. Channel check sources is always enabled. Change Advanced Co-Processor Platform Adapter to ARTIC960 Co-Processor Platform Adapter. Device I/O Address The Device I/O Address field is a six-bit field that selects the I/O address of the ARTIC960 Co-Processor Platform Adapter. The six bits represent bits 15 through 10 of the I/O address. Address bits 15, 14, and 13 are in POS register 5. Address bits 12, 11, and 10 are in POS subaddress 100 (POS register 3A). <"1C00H-1C1FH">, 3C00-3C1F, 5C00-5C1F, 7C00-7C1F, 9C00-9C1F, BC00-BC1F, DC00-DC1F, FC00-FC1F Interrupt Level The interrupt level is the prioritized interrupt request line on which the ARTIC960 Co-Processor Platform Adapter will interrupt the system. The highest to lowest interrupt priorities are as follows: 9, 10, 14, 7. The interrupt level may be shared with another adapter. The preferred interrupt level is 7. <"Level 7">, 10, 14, 9 Primary Arbitration Level This field is the primary arbitration level for the ARTIC960 Co-Processor Platform Adapter Busmaster DMA transfers. An arbitration level of 0 has the highest priority, and increasing levels have corresponding decreased priority <"Level E">, D, C, B, A, 9, 8, 3, 2, 1 Streaming Data This field enables or disables the Streaming Data feature of the ARTIC960 Co-Processor Platform Adapter as both a Bus Master and a Slave. The default state of this field is disable, which causes the adapter to use the basic data transfer procedures. When enabled, the streaming data procedure is supported. <"Disabled">, Enabled Selected Feedback Return This field enables or disables the checking and reporting of loss of Selected Feedback Return by the Bus Master of the ARTIC960 Co-Processor Platform Adapter. The default state of this field is disable. <"Disabled">, Enabled Address and Data Parity This field enables or disables the address and data parity checking and generation by the ARTIC960 Co-Processor Platform Adapter. The default state of this field is disable. <"Disabled">, Enabled Asynchronous/Synchronous Channel Check This field indicates the mode that the ARTIC960 Co-Processor Platform Adapter uses when driving -CHCK active. When synchronous mode is selected, -CHCK is signaled by the adapter with a pulse on -CHCK during the data transfer cycles. When selected for asynchronous mode, the adapter drives -CHCK active asyschronously to a data transfer, i.e -CHCK remains active until reset by the system master. The default state of this field is Asynchronous. <"Asynchronous">, Synchronous 1st Shared Storage Window Location There are two independent windows into the RAM on the ARTIC960 Co-Processor Platform Adapter. This is the first window which is located in the ROM/RAM area. The size of this window can be either 8 KBytes or 16 KBytes 8K window. <"DE000H-DFFFFH, 8K Window">, DC000-DDFFF, DA000-DBFFF, D8000-D9FFF, D6000-D7FFF, D4000-D5FFF, D2000-D3FFF, D0000-D1FFF, CE000-CFFFF, CC000-CDFFF, CA000-CBFFF, C8000-C9FFF, C6000-C7FFF, C4000-C5FFF, C2000-C3FFF, C0000-C1FFF 16K window. <"DC000H-DFFFFH, 16K Window">, D8000-DBFFF, D4000-D7FFF, D0000-D3FFF, CC000-CFFFF, C8000-CBFFF, C4000-C7FFF, C0000-C3FFF 2nd Shared Storage Window Location (This field will call the ADP) There are two independent windows into the RAM on the ARTIC960 Co-Processor Platform Adapter. This is the second window which is located above 1 MEG. The size of this window is equal to the amount of RAM installed on the adapter <"Above 1M, Window=Memory Size"> |
