SGI Micro-Channel IRISVISION Adapter
"sabine" or the "High Performance 3D Color Graphics
Very Unofficial IrisVison Home Page By Roger Brown
Application Programming Interface (Same as below, but HTML)
Graphics Library Programming
Guide, Volume I
Graphics Library Programming
Guide, Volume II
IrisVision drivers and related software:
* Here are copies of the IrisVision
software, 24-bit color demos, and IrisView
DXF file viewer:
o The SGI v2.00 disk images -
5.6MB pkzip archive.
o The Pellucid 2.10 (beta) disk images (w/o IrisView) - 2.9MB pkzip archive.
+ Copy of the GL.386 file for
the above (86KB).
* Autodesk ADI
Combined Display/Rendering driver:
o Click here to download the ISA version
of the driver (550Kb)
o Click here to download the MCA version
of the driver (550Kb)
* Windows 3.x
display driver disk image.
* IrisVision GL
Software Developer's Kit v 2.10 disk image (1 Mb).
o You'll need to set a few environment variables, this file has some example
o Here's a link
to on-line version for all the IrisGL API.[outdated]
Note to PS/2 MicroChannel Users:
* The Windows display driver
(above) are for the ISA IRISVISION card, only. Unfortunately, it seems
when Pellucid developed this driver, they did not include support for the
MCA version of the board set.
IrisVision Technical Reference.
About 700 pages.
IrisVision Block Diagram
MEV2 24 Bit
Video Option FRU: 71F1114
This card supplies the additional bitplanes
of memory to bring the system to 24 bits per pixel of normal framebuffer
in addition to 2 additional overlay/popup bitplanes and 2 additional window
ID planes, for a total of 32-bits per pixel. A fully configured frame buffer
has a total of 1280x1024*(32/8) or 5MB of video RAM (VRAM) implemented
in 256Kx8 ICs.
|P4 RGB Video
P5 Video Bus
P6 Utility Bus
P7 Pixel Bus
U1 MEV 1112
U15-39 Toshiba TC524258AJ-10
U61-63 Brooktree Bt457KPJ125
U41,45,49,53,57 SGI XMAP2 L1A5081
You'll notice that the VRAM is laid
out in a 5xN array of chips. Each chip supplies 256 horizontal pixels (1280/5
= 256). However, to achive greater performance, the raster engine chip
is designed to write up to 5 pixels at a time, so the five VRAM chips are
interleaved; the first supplies pixels 1, 6, 11, etc. the second 2, 7,
12, etc. and so on.
MZB1 24 Bit Video
Buffer FRU: 42F6889
This is the optional 24-bit hardware
z-buffer card. The function of the z-buffer is to perform hidden surface
removal via a depth test mechanism. In the traditional application, each
pixel's "Z" coordinate value is tested against the value already present
in that location in the z-buffer. If it is smaller (i.e. closer to the
eye) the pixel is updated with the current value and the z-buffer is updated.
By controlling the z-buffer operation, a number of other useful operations
|P8 Z Buffer Utility Bus
U16-U45 TI TMS44C256DJ -10
or Toshiba TC514256AJ-10
|U60 MZB 7923
For non-3D applications, the z-buffer
can be used as an off-screen memory buffer for saving the contents of the
normal framebuffer. As no host to adapter memory transfer takes place,
this operation is very fast. The z-buffer is implemented in dynamic RAM
(DRAM) and consists of 3.75 MB of DRAM.
Geometry Engine FRU: 42F6842
This is the MicroChannel Geometry Engine.
It is based upon the HQ integer processor from SGI (rated at 10 MIPS) and
the Weitek XL-3132 floating point processor (rated at 20 MFLOPS). The geometry
engine provides the host interface, handles DMA operations, and handles
all the matrix operations, lighting and coordinate transformations.
U15 SGI L1A5205
U25 SGI L1A3578
U64 MGE 7951
U67 SGI L1A4252
Raster Video FRU: 71F1151
This is the MicroChannel Raster
Video Engine. It is based upon the RE 2.1 raster engine chip from SGI.
The raster engine provides all the per-fragment and -pixel operations.
It also contains the raster scanning hardware and video signal generation
circuitry. It only obtains power and ground from the bus, no other bus
signals are used. In addition to the two ribbon cables from the Geometry
Engine, a third connection services the Genlock features of the Raster
On the card edge connector, are
the VGA passthrough connector and the HiRes video output connector. The
Raster Video card contains the basic 8-bitplanes of framebuffer memory
as well as 2 bitplanes of overlay framebuffer and 2 bits of window ID bitplanes,
for a total of 12 bpp.
This card features an RGB video
output connector (large w/plug-style connectors) and a genlock input/output
connector (15-pin DSUB). If you happen to find an IBM-style card set and
need the RGB video cable, let me know. (I'll pass it on to Roger).
The MZB1 plugs onto the back (circuitboard
side) of this card (use the short screws). The MEV2 plugs on to the front
side (component side) of the card (use long screws).
Connector cable (wide) 53F3271 80 pin .025 pitch HPDB
Connector cable (narrow) 53F3272 40 pin .025 pitch HPDB
Removing Connector Cable
Squeeze the metal clips on the ends of the connectors
and pull the connector off the header.
Plugging Connector Cables Back On
Sqeeze the metal clips so that the loose ends of the clip
enter the catch on the header.
The following block diagram is derived from the IrisVision Block
Diagram on The
Very Unofficial IrisVison Home Page
IrisVision Board Functional
Stolen from Roger
Very Unofficial IrisVison Home Page
The IrisVision hardware is nearly identical to the
graphics sub-system in the SGI Personal Iris workstation introduced in
1988. The hardware supports a 5th generation geometry processing pipeline,
the GE5, an 8 or 24 bit per pixel frame buffer, and a 24-bit per pixel
z-buffer for hidden surface removal. The card set implements in hardware,
the entire IrisGL graphics Application Programming Interface (API).
Notable differences from the Personal Iris graphics are:
Uses 256K VRAM instead of 64K VRAM for reduced
Has a 3 color cursor instead of 1 color for
Has VGA pass-through capability for PC compatibility
The card has a rich set of video and rendering modes consistent with
the Personal Iris.
Origins of the IrisVision
The product came to life originally as an OEM graphics
board set based upon the VME bus in the Personal IRIS . Later, IBM approached
SGI to develop a Micro Channel Architecture (MCA) version of the card for
use in their newly introduced RS-6000 Unix workstation. IBM licensed the
MCA card design as well as the IrisGL graphics library from SGI.
In the process of testing the product, it was discovered
that an IBM PS/2 model 70 personal computer running OS/2 could be used
to run diagnostics and test programs on the card much easier than using
the RS-6000. So a minimal device driver was written for the card and soon
IBM was shipping product. (Ed.
Roger Brown can't find the "minimal OS/2 drivers" and he works for SGI.)
At some point, the light went off in someone's head; "Why
don't we sell this board set for use in PCs?". IrisVision was born. Initially,
the MCA card was re-designed to offer some features critical for the PC
market, including standard 15-pin VGA-style video output and a 15-pin VGA
passthrough input connector. The IBM genlock connector was moved to the
top of the card, and stereo display signals were also brought out to the
VGA passthrough connector. The card occupied 1 32-bit MCA slot and an adjacent
16/32 bit slot. One or two daughter boards provided framebuffer and z-buffer
Work then began on the design of an Industry Standard
Architecture (ISA or AT-bus) version of the card. It would occupy 2 16-bit
ISA slots and use the identical daughter cards as the MCA (and IBM) versions
of the board set.
The IrisGL API is implemented in a C-language library
developed with the Metaware High-C 32-bit C compiler and the PharLap 32-bit
DOS-Extender. It was designed to run in a full screen DOS environment.
At the time, M/S Windows did not offer a 32-bit programming environment,
so the PharLap DOS-Extender technology was the most sophisticated solution
available. It features full 32-bit virtual addressing (2 GB application
space), virtual memory support, and seamless integration of real and protected
mode programs. The MetaWare High-C compiler is ANSI compatible and is just
the ticket for compiling Unix source code to run under DOS-Extender on
the IrisVision card.
|Pixel Clock (MHz)
|Horizontal Freq (KHz)
|Frame Rate (Hz)
|Field Rate (Hz)
|Line Period (uS)
|Front Porch (uS)
|Sync Width (uS)
|Back Porch (uS)
|Front Porch (mS)
|Sync Width (mS)
|Back Porch (mS)
ADF Sections AdapterId
8EE6h "SGI Micro-Channel IRISVISION Adapter"
Determines the interrupt level used by IRISVISION Adapter.
<" Level 2 " >,
3, 4, 5, 6, 9, 10, 11, 12
Memory Mapped I/O Address Range
Determines the range of Memory Mapped I/O addresses used
by the IRISVISION Adapter. The addresses in this range cannot be
used by any other installed device.
<" 0C0000 to 0C7FFF " >,
0C8000 to 0CFFFF, 0D0000 to 0D7FFF, 0D8000 to 0DFFFF
Determines the bus arbitration level used.
<" Arb Level 1 ">, 0, 2, 3,
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
Silicon Graphics, SGI, OpenGL, Personal Iris, and IrisVision
are registered trademarks of Silicon Graphics, Inc.
I usually don't mess with Trademarks, but that of SGI is very
Info just was too damn good. Class act, SGI! I wish M$ and their bloodsucking
shark team was only a tenth as smooth as you! Sorry, SGI, Netscape makes
them durned TM's and Registered marks look like ASCII.
SGI does not endorse any of the information on this page.
They retain all rights to their trademarks. Further, this information is
furnished on an "As Is" basis. If you fry your monitor or card, that's
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