Q Type 4 Complex
Rf90954a.exe Reference disk for Type 4 Complexes
Rd9095a.exe Common Diagnostics for all 859x
/ 959x Systems
Type 4 Common Devices
Memory supported, cache, features
Support for Convenience Partition
on >3.94GB Drives
Flash BIOS 05 from
BIOS 03 or less
BIOS Level Revison
"Q" / Upgrade Pentium 66 MHz 92F0120
Pentium Overdrive 133MHz (POD133/120)
Q Upgrade Success! (Tim Clarke reutrns!)
496 vs. 497 Cache Controller
"Q" / Upgrade Pentium 66
Diagnostics Link to operator panel
ROM bank switch
OS1 66 MHz oscillator. CPU Bus
10G3407 Flash BIOS, Odd ?
10G3372 Flash BIOS Even ?
U10, 12, 15, 16, 18 82491-66
Socket 4 5v for Pentium 60 or 66
A82496-66 Cache controller
50G8192 Unknown DMA Controller?
LT LT1085CT Voltage Regulator
C39 22uF capacitor
not present on P complex. Possible power filter?
LEDs. CR1 lights momentarily at the start of POST, then turns off, CR2
stays on during POST, then turns off..
Present on some P60/P66 complexes. Function unknown
A82496-66 Cache controller
Outline Left of CPU
Unknown. Maybe for a component that used four mounting posts to match the
pattern. The right pair have thick PCB traces going to them. Maybe a VRM?
Q Complex Back
OS2 40 MHz MCA Bus Clock
Min/Max on system board: 8/64MB Parity, 8/256MB ECC
RAM: DRAM (PS/2 72-pin SIMM, ECC or Parity) 70ns
Cache: 8kb L1, 256kb L2 (P60, P66, P90)
* 40 MB per second streaming
* Error Checking and Correcting (ECC)
* 256KB Level 2 memory cache (write-through) on Pentium complexes
* 20 MHz DMA; 32 bit DMA can directly address all memory
* DMA supports Subsystem Control Block.
* Faster bus arbitration (than Base 1) for busmaster performance.
* Enhanced Dual Path Memory
* Subsystem Control Block
* Vital Product Data
* Synchronous Channel Check
* Data bus parity support
* A logging facility is provided (for ECC or system errors)..
Intel Pentium Overdrive
I dug through craploads of old Intel documents today,
and found my notes from Intel (circa '95) for the Pentium Overdrive 133MHz
Written in plain ingles, the Intel doc says: "will not
support the 82496 Cache Controller and 82491 Cache SRAM chip set"
Additionally, the documentation states that the POD133
is designed to support _PCI_ chipsets.
Some other notes:
- IU, IV, and IBT plus have been removed
- branch trace pins (BT[3:0]) have been removed (no execution
- breakpoint pins (BP[3:0]) have been redefined such that each
assertion of one of these pins indicates that 1 to N BP matches occurred,
where N =core/bus frequency ratio
- STI/CLI (restore/clear interrupts) are each 2 clocks shorter
Q Upgrade Success
Tim Clarke said:
Without going into too much analysis as to WHY its
working. I have this up and running reliably, so far. Using a T4-P66 complex
previously Flashed to BIOS Level 10, an 82497 cache controller from a T4
P90 complex and a stock PODP5V120/133 Overdrive for Socket 4 (Ed.
square 21x21, 237pin PGA (pin-grid-array), stop beating me, Tim!))
It threw the odd "1047000 221" error (cache/memory-related?)
early in the power-on, auto-reconfigure, set date&time, auto-reboot
song and dance but doesn't seem to do that anymore. Maybe there are some
devious POS-stored auto-tuned cache-control/memory-access related parameters,
but hey, I'm not complaining.
496 vs. 497 Cache
From Dr. Jim Shorney
Overdrive processors are not compatible with the '496
cache controller on the P60/66 complexes. However... I swapped
out the '496 cache controller on mine for a borrowed '497 (well heatsinked)
and was able to boot DOS with a POD 133 on my P60 (overclocked to 66).
It wasn't entirely stable, and would not boot OS/2 Warp 4.0 or NT 4.0.
The Powerleap PL54C interposer was still dead in this configuration.
There may yet be hope, I haven't tried the Powerleap with anything other
than an Intel 166 yet, and I may also downclock the complex back to 60
MHz and see what happens. There may yet be hope...
The '497 reportedly has a 3.3v core,
but it seemed to run stable and reliable for several hours with the stock
P60 CPU in my system in place of the 5v '496. I briefly looked
over the docs this afternoon (712 pages, wow...). Seems the '497 is still
a 5v part, it is the I/O buffers that connect to the CPU that are 3.3v.
This probably explains in part why the chip doesn't self-destruct in the
'496 socket. It also seems to invalidate the need for an interposer,
since the P60/66 I/O is 5v anyway and the buffers would have to run at
5v to interface at all with the CPU. This brings up the question
of noise immunity, though - will circuits designed to run at 3.3v logic
levels be more or less sensitive to noise or poor signal quality when run
at 5v? Inquiring minds want to know.
From Tony Ingenoso
I suspect noise is going to be less of a problem
at higher voltages Jim. In theory, the voltage range for correct
operation would be wider(particularly for CMOS). The only reason
I ever saw (other than laptop applications) for the drive to lower voltages
was to limit heat as the gate counts and frequencies went up. CMOS
parts like high voltages -- you can crank clock speeds faster with higher
voltages(the standard overclockers trick). Discrete type CMOS parts
can often be run as high as 20V and work fine. The downside is that
its power characteristics start approaching those of TTL at the higher
speeds (and heat goes up). If the only nominally 3.3V sections of
the cache controller are the line drivers/buffers, there's probably not
going to be enough stuff getting overvoltaged to make any significant difference
in the power draw.
9595 Server 95 (AKA "Server 95 566")
9595-0QT - P66, 16/256MB (ECC), 1GB SCSI-2 F/W, 2.88,
9595-0QTF - As above - Canadian French
9595-0QV - P66, 16/256MB (ECC), 2GB SCSI-2 F/W, 2.88
9595-PQG - Pentium 66, 16/256MB (ECC), 540MB SCSI-2 F/W, 2.88
9595-PQT - P66, 16/256MB (ECC), 1GB SCSI-2 F/W, 2.88
9595 Server 95 Array Models (Also called 95A)
9595-3QG - P66, 16/256MB (ECC), 3 x 540MB SCSI-2 F/W, 2.88
9595-3QT - P66, 16/256MB (ECC), 3 x 1GB SCSI-2 F/W, 2.88
NOTE: SERVER 95 -PQG &
-PQT models came with MGA Ultima Video Graphics Adapter, CD-ROM-II drive,
and 3-button mouse